Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. FPGA Simulation Basics 2. Siemens EDA QuestaSim* Simulator Support 3. Synopsys VCS* and VCS MX Support 4. Aldec Active-HDL and Riviera-PRO Support 5. Cadence Xcelium* Parallel Simulator Support 6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Quartus® Prime Pro Edition User Guides
1. FPGA Simulation Basics x
1.1. FPGA Simulation Essential Elements 1.2. Overview of Simulation Tool Flow 1.3. Simulation Tool Flow 1.4. Supported Simulation Flows 1.5. Supported Hardware Description Languages 1.6. Supported Simulation Types 1.7. Supported Simulators 1.8. Post-Fit Simulation Support by FPGA Family 1.9. Automating Simulation with the Run Simulation Feature 1.10. Intel FPGA Simulation Basics Revision History
1.2. Overview of Simulation Tool Flow x
1.2.1. Compilation Stage 1.2.2. Elaboration Stage 1.2.3. Simulation Stage
1.3. Simulation Tool Flow x
1.3.1. Specifying Logical Libraries 1.3.2. Compiling Files Into Library Directories 1.3.3. The Quartus® Prime Simulation Library 1.3.4. Understanding Elaboration 1.3.5. Commands To Configure and Run Simulation 1.3.6. FPGA Simulation Generic Workflow
1.3.1. Specifying Logical Libraries x
1.3.1.1. Why Do We Need Logical Library Names?
1.3.2. Compiling Files Into Library Directories x
1.3.2.1. Inputs to Compilation Commands 1.3.2.2. Order of Files for Compilation Commands 1.3.2.3. Compilation Command Line Options 1.3.2.4. Module Definitions in Library Directories
1.3.3. The Quartus® Prime Simulation Library x
1.3.3.1. The Quartus® Prime Simulation Library Compiler 1.3.3.2. Running the Simulation Library Compiler in a Terminal 1.3.3.3. Running the Simulation Library Compiler in the GUI 1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
1.3.4. Understanding Elaboration x
1.3.4.1. Elaboration Binding Phase 1.3.4.2. Elaboration Checks 1.3.4.3. Elaboration Options
1.9. Automating Simulation with the Run Simulation Feature x
1.9.1. Setting Up the Run Simulation Feature 1.9.2. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line)
1.9.1. Setting Up the Run Simulation Feature x
1.9.1.1. Installation Paths for Supported EDA Simulators (EDA Tool Options Page) 1.9.1.2. Simulation Options (Board and IP Settings Page) 1.9.1.3. Simulation Flow Settings (EDA Tool Settings Page) 1.9.1.4. More EDA Netlist Writer Settings (EDA Tool Settings Page)
1.9.2. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) x
1.9.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode) 1.9.2.2. Optional Simulation Settings for Run Simulation (Batch Mode) 1.9.2.3. Launching Simulation with the Run Simulation Feature 1.9.2.4. Running RTL Simulation using Run Simulation 1.9.2.5. Output Directories and Files for Run Simulation
2. Siemens EDA QuestaSim* Simulator Support x
2.1. Quick Start Example (QuestaSim* with Verilog) 2.2. QuestaSim* Simulator Guidelines 2.3. Using the Qrun Flow 2.4. QuestaSim* Simulation Setup Script Example 2.5. Sourcing QuestaSim* Simulator Setup Scripts 2.6. Unsupported Features 2.7. Siemens EDA QuestaSim* Simulator Support Revision History
2.2. QuestaSim* Simulator Guidelines x
2.2.1. Passing Parameter Information from Verilog HDL to VHDL 2.2.2. Viewing Simulation Messages 2.2.3. Generating Signal Activity Data for Power Analysis 2.2.4. Viewing Simulation Waveforms
2.3. Using the Qrun Flow x
2.3.1. Specifying Simulation File Generation Settings 2.3.2. Generating the Simulation Model and Setup Scripts 2.3.3. Generating the Testbench System 2.3.4. Generating Example Design Simulation Files 2.3.5. Recommendations for Using Qrun
3. Synopsys VCS* and VCS MX Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS and VCS MX Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 3.5. Sourcing Synopsys VCS* Simulator Setup Scripts 3.6. Synopsys VCS* and VCS MX Support Revision History
4. Aldec Active-HDL and Riviera-PRO Support x
4.1. Quick Start Example (Active-HDL VHDL) 4.2. Aldec Active-HDL and Riviera-PRO Guidelines 4.3. Using Simulation Setup Scripts 4.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 4.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5. Cadence Xcelium* Parallel Simulator Support x
5.1. Using the Command-Line Interface 5.2. Generating Simulator Setup Script Templates 5.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 5.4. Cadence Xcelium* Parallel Simulator Support Revision History
Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides

1.9.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)

There are both required and optional setting for use of Run Simulation in batch mode.

The following steps describe specifying the required simulation settings for use of Run Simulation in batch mode:

  1. Set the compatible EDA Simulator executable path. For example: 
    set_user_option -name EDA_TOOL_PATH_ QUESTA_INTEL /<simulator install
 path>/questa_fe_tag/24.1/92/linux64/linux_x86_64

set_user_option -name EDA_TOOL_PATH_ QUESTASIM /<simulator install 
 path>/eda/mentor/questasim/2023.4/linux64/linux_x86_64

set_user_option -name EDA_TOOL_PATH_ VCS /<simulator install
 path>/eda/synopsys/vcsmx/U-2023.03-1/linux64/suse/bin

set_user_option -name EDA_TOOL_PATH_ VCS_MX /<simulator install
 path>/eda/synopsys/vcsmx/U-2023.03-1/linux64/suse/bin

set_user_option -name EDA_TOOL_PATH_ACTIVEHDL <drive letter>:\<simulator install 
 path>\eda\aldec\activehdl\13.0\windows64\bin

set_user_option -name EDA_TOOL_PATH_RIVIERAPRO /<simulator install 
path>/eda/aldec/riviera/2023.04.082/linux64/bin

set_user_option -name EDA_TOOL_PATH_ XCELIUM /<simulator install 
  path>/eda/cadence/xcelium/23.03.003/linux64/suse/tools.lnx86/bin
  2. Specify your supported EDA Simulator and HDL: 
    set_global_assignment -name EDA_SIMULATION_TOOL 
"<simulator> (HDL)"

    If not set, the following is the default setting:

    set_global_assignment -name EDA_SIMULATION_TOOL 
"Questa Intel FPGA (Verilog)"
    Table 12.  Settings for EDA Simulator and HDL
    Simulator Verilog VHDL
    Questa* Intel® FPGA Edition Questa Intel FPGA (Verilog) Questa Intel FPGA (VHDL)
    QuestaSim* QuestaSim (Verilog) QuestaSim (VHDL)
    VCS* VCS N/A
    VCS* MX VCS MX (Verilog) VCS MX (VHDL)
    Active-HDL* Active-HDL (Verilog) Active-HDL (VHDL)
    Riviera-PRO* Riviera-PRO (Verilog) Riviera-PRO (VHDL)
    Xcelium* Xcelium (Verilog) Xcelium (VHDL)
  3. Set the testbench and simulation file (if any) names, as well as the section ID (arbitrary). This is a multi-value assignment. The following shows an example with the testbench file 1 as the top-level testbench file: 
    set_global_assignment -name EDA_TEST_BENCH_FILE <testbench file 1> 
-section_id testbenchSet
set_global_assignment -name EDA_TEST_BENCH_FILE <testbench file 2> 
-section_id testbenchSet
set_global_assignment -name EDA_TEST_BENCH_FILE <testbench file 3> 
-section_id testbenchSet
  4. Set the top-level module name in the top testbench file. 
    set_global_assignment -name EDA_TEST_BENCH_TOP_MODULE <testbench top module name>
 -section_id testbenchSet
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