Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

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ID 683871
Date 9/01/2020
Public
Document Table of Contents
Document Table of Contents x
1. CvP Initialization in Intel® Arria® 10 2. Design Considerations for CvP Initialization in Intel® Arria® 10 3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10 4. CvP Driver and Registers 5. Partial Reconfiguration over PCI Express in Intel® Arria® 10 6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10 7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
1. CvP Initialization in Intel® Arria® 10 x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Support for Intel® Arria® 10 Devices 1.4. CvP Initialization 1.5. CvP Compression and Encryption Features 1.6. CvP Pins
2. Design Considerations for CvP Initialization in Intel® Arria® 10 x
2.1. Designing CvP for an Open System 2.2. Designing CvP for a Closed System
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10 x
3.1. Generating the Synthesis HDL Files for Intel® Arria® 10 PCI Express IP Core 3.2. Setting up the CvP Parameters in Device and Pin Options 3.3. Compiling the Design 3.4. Splitting the SOF File 3.5. Bringing up the Hardware
3.5. Bringing up the Hardware x
3.5.1. Installing Jungo WinDriver in Windows Systems 3.5.2. Installing Jungo WinDriver in Linux Systems 3.5.3. Installing Open Source CvP Driver in Linux System 3.5.4. Modifying MSEL/DIP switch on Intel® Arria® 10 Dev-Kit 3.5.5. Programming CvP Images
4. CvP Driver and Registers x
4.1. CvP Driver Support 4.2. CvP Driver Flow 4.3. VSEC Registers for CvP
4.3. VSEC Registers for CvP x
4.3.1. Altera-defined Vendor Specific Capability Header Register 4.3.2. Altera-defined Vendor Specific Header Register 4.3.3. Altera Marker Register 4.3.4. CvP Status Register 4.3.5. CvP Mode Control Register 4.3.6. CvP Data Registers 4.3.7. CvP Programming Control Register 4.3.8. Uncorrectable Internal Error Status Register 4.3.9. Uncorrectable Internal Error Mask Register 4.3.10. Correctable Internal Error Status Register 4.3.11. Correctable Internal Error Mask Register
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10 x
5.1. Benefits of Using PR over PCI Express 5.2. PR over PCIe System 5.3. Partial Reconfiguration Design Flow 5.4. Partial Reconfiguration IP Core
1. CvP Initialization in Intel® Arria® 10
2. Design Considerations for CvP Initialization in Intel® Arria® 10
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10
4. CvP Driver and Registers
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10
6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10
7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide

7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide

Date Changes
2020.09.01
  • Added information about custom CvP driver for Linux in section Bringing Up the Hardware.
  • Added a note about the availability of Jungo WinDriver in the following sections:
    • Bringing Up the Hardware
    • CvP Driver Support
  • Added new section Installing Open Source CvP Driver in Linux System.
  • Added steps to program the core image using the open source Linux driver in section Programming CvP Images.
2019.10.11
  • Added a command to generate CvP periphery image (.jam) file for the JTAG configuration in section Splitting the SOF File.
  • Clarified the use *.pof file for the Passive Serial or Fast Passive Serial configuration mode.
  • Implemented Intel rebranding.
2019.04.12 Corrected the Figure: PCIe Timing Sequence in CvP Initialization Mode for link training state.
2016.10.31
  • Changed the document title from 'Arria CvP Initialization and Partial Reconfiguration via Protocol User Guide' to 'Arria CvP Initialization and Partial Reconfiguration over PCI Express User Guide'.
  • Removed the topic Autonomous Mode, instead refer to the Intel® Arria® 10 Avalon-MM/ST Interface for PCIe Solutions User Guide.
  • Added the pin descriptions for INIT_DONE and CONF_DONE.
  • Corrected the PCIe Timing Sequence diagram for CvP initialization.
  • Added the timeout value for CvP_CONFIG_READY in the Figure: CvP Driver Flow.
  • Added the topic Partial Reconfiguration Design Flow to the Chapter: Partial Reconfiguration over Protocol in Intel® Arria® 10 .
  • Removed the Design Planning for PR over PCI Express in Intel® Arria® 10 chapter. Instead refer to Creating a Partial Reconfiguration Design.
  • Removed the following topics from Chapter: Understanding Design Steps for PR over PCI Express in Intel® Arria® 10 :
    • Creating a Qsys design
    • Creating User Logic and Top Level File
    • Creating PR Partition
    • Generating Base SOF/RBF Bitstreams
    • Creating PR Revision
    • Generating PR Bitstreams
    • Bringing Up the Hardware
  • Fixed assorted typos and formatting issues.
2016.05.02 Initial release
Level Two Title