Visible to Intel only — GUID: uoa1650826051407
Ixiasoft
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204B Design Example
4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide
Visible to Intel only — GUID: uoa1650826051407
Ixiasoft
3.5. F-Tile JESD204B Design Example Status and Control Registers
The F-Tile JESD204B design example registers use byte-addressing (32 bits).
Refer to the F-Tile JESD204B Registers section in the F-Tile JESD204B Intel® FPGA IP User Guide.
Related Information