F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 11/29/2023
Public
Document Table of Contents

2.6. Hardware Testing

In the hardware design example, you can program the IP core in internal serial loopback mode and generate traffic on the transmit side that loops back through the receive side.

Follow the procedure at the provided related information link to test the design example in the selected hardware.