F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

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ID 750200
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile 25G Ethernet Single-Channel Design Example 3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration 4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives 5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile 25G Ethernet Single-Channel Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Single-Channel Design Example with Dynamic Reconfiguration
3.5. Hardware Testing x
3.5.1. Test Procedure
1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench

You can compile and simulate the design by running a simulation script from the command prompt.
Ensure you have completed the Support-Logic Generation to generate the tile files required for simulation.
  1. At the command prompt, change the testbench simulating working directory: cd <design_example_dir>/ex_25g/sim.
  2. Run the IP setup simulation:ip-setup-simulation -quartus-project=../../compilation_test_design/alt_eth_25g.qpf
  3. At the command prompt, change the working directory to <design_example_dir>/example_testbench.
  4. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
    Table 3.  Steps to Simulate the Testbench
    Simulator Instructions
    VCS* In the command line, type sh run_vcs.sh
    QuestaSim* In the command line, type vsim -do run_vsim.do -logfile vsim.log

    If you prefer to simulate without bringing up the QuestaSim* GUI, type vsim -c -do run_vsim.do -logfile vsim.log

    Cadence - Xcelium* In the command line, type sh run_xcelium.sh
A successful simulation ends with the following message: 
Simulation Passed.
or 
Testbench complete.
After successful completion, you can analyze the results.
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