F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

Download PDF
ID 750200
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile 25G Ethernet Single-Channel Design Example 3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration 4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives 5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile 25G Ethernet Single-Channel Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Single-Channel Design Example with Dynamic Reconfiguration
3.5. Hardware Testing x
3.5.1. Test Procedure
1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

1.5. Compiling and Configuring the Design Example in Hardware

The 25G Ethernet Intel FPGA IP core parameter editor allows you to compile and configure the design example on a target development kit.
To compile and configure a design example on hardware, follow these steps:
  1. Launch the Intel® Quartus® Prime Pro Edition software and select Processing > Start Compilation to compile the design.
  2. After you generate an SRAM object file .sof, follow these steps to program the hardware design example on the Intel Agilex® 7 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Intel Agilex® 7 board to your Intel® Quartus® Prime Pro Edition session.
    5. Ensure that Mode is set to JTAG.
    6. Select the Intel Agilex® 7 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.
Level Two Title