Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.8. Recommended HDL Coding Styles Revision History

The following revisions history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2021.10.04 21.3
  • Added new Inferring FIFOs in HDL Code topic and linked to FIFO Intel FPGA IP User Guide.
  • Added new Dual Clock FIFO Example in Verilog HDL topic.
  • Added new Dual Clock FIFO Timing Constraints topic.
2021.06.21 21.2
  • Updated Inferring Shift Registers in HDL Code for Intel® Stratix® 10 and Intel® Agilex™ devices.
  • Updated wording of Controlling RAM Inference and Implementation for clarity.
2019.09.30 19.3
  • Updated Simple Dual-Port Synchronous RAM with Byte Enable examples.
  • Updated True Dual-Port Synchronous RAM examples.
  • Updated Verilog HDL Single-Bit Wide Shift Register example from 64 to 69 bits.
  • Updated VHDL Single-Bit Wide Shift Register example from 67 to 69 bits.
  • Updated Verilog HDL 8-Bit Wide Shift Register with Evenly Spaced Taps from 64 to 254 bits.
2018.09.24 18.1
  • Added "State Machine Power-Up" topic.
  • Updated "Designing with Low-Level Primitives" to remove support for carry and cascade chains using CARRY, CARRY_SUM, and CASCADE primitives.
  • Renamed topic: "Use the Device Synchronous Load (sload) Signal to Initialize" to "Initialize the Device with the Synchronous Load (sload) Signal"
2017.11.06 17.1
  • Described new no_ram synthesis attribute.
2017.05.08 17.0
  • Updated example: Verilog HDL Multiply-Accumulator
  • Updated information about use of safe state machine.
  • Revised Check Read-During-Write Behavior.
  • Revised Controlling RAM Inference and Implementation.
  • Revised Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior.
  • Revised Single-Clock Synchronous RAM with New Data Read-During-Write Behavior.
  • Updated and moved template for VHDL Single-Clock Simple Dual Port Synchronous RAM with New Data Read-During-Write Behavior.
  • Revised Inferring ROM Functions from HDL Code.
  • Removed example: VHDL 8-Bit Wide, 64-Bit Long Shift Register with Evenly Spaced Taps.
  • Removed example: Verilog HDL D-Type Flipflop (Register) With ena, aclr, and aload Control Signals
  • Removed example: VHDL D-Type Flipflop (Register) With ena, aclr, and aload Control Signals
  • Added example: Verilog D-type Flipflop bus with Secondary Signals
  • Removed references to 4-input LUT-based devices.
  • Removed references to Integrated Synthesis.
  • Created example: Avoid this VHDL Coding Style.
2016.10.31 16.1
  • Provided corrected Verilog HDL Pipelined Binary Tree and Ternary Tree examples.
  • Implemented Intel rebranding.
2016.05.03 16.0
  • Added information about use of safe state machine.
  • Updated example code templates with latest coding styles.
2015.11.02 15.1
  • Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0 Added information and reference about ramstyle attribute for sift register inference.
2014.12.15 14.1 Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Optimization Settings to Compiler Settings.
2014.08.18 14.0.a10
  • Added recommendation to use register pipelining to obtain high performance in DSP designs.
2014.06.30 14.0 Removed obsolete MegaWizard Plug-In Manager support.
November 2013 13.1 Removed HardCopy device support.
June 2012 12.0
  • Revised section on inserting Altera templates.
  • Code update for Example 11-51.
  • Minor corrections and updates.
November 2011 11.1
  • Updated document template.
  • Minor updates and corrections.
December 2010 10.1
  • Changed to new document template.
  • Updated Unintentional Latch Generation content.
  • Code update for Example 11-18.
July 2010 10.0
  • Added support for mixed-width RAM
  • Updated support for no_rw_check for inferring RAM blocks
  • Added support for byte-enable
November 2009 9.1
  • Updated support for Controlling Inference and Implementation in Device RAM Blocks
  • Updated support for Shift Registers
March 2009 9.0
  • Corrected and updated several examples
  • Added support for Arria II GX devices
  • Other minor changes to chapter
November 2008 8.1 Changed to 8-1/2 x 11 page size. No change to content.
May 2008 8.0

Updates for the Intel® Quartus® Prime software version 8.0 release, including:

  • Added information to “RAM
  • Functions—Inferring ALTSYNCRAM and ALTDPRAM Megafunctions from HDL Code” on page 6–13
  • Added information to “Avoid Unsupported Reset and Control Conditions” on page 6–14
  • Added information to “Check Read‑During‑Write Behavior” on page 6–16
  • Added two new examples to “ROM Functions—Inferring ALTSYNCRAM and LPM_ROM Megafunctions from HDL Code” on page 6–28: Example 6–24 and Example 6–25
  • Added new section: “Clock Multiplexing” on page 6–46
  • Added hyperlinks to references within the chapter
  • Minor editorial updates