AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

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ID 683167
Date 5/19/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Functional Description 1.4. Hardware Testing 1.5. TCL Script 1.6. Interface Signals 1.7. Configuration Registers and Status Registers 1.8. Regenerating Triple-Speed Ethernet Intel® FPGA IP 1.9. Document Revision History for AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1.3. Functional Description x
1.3.1. Design Components 1.3.2. Clocking Scheme 1.3.3. Reset Scheme
1.4. Hardware Testing x
1.4.1. Test Case—Internal MAC Loopback 1.4.2. Test Case— Avalon® Streaming Reverse Loopback
1.5. TCL Script x
1.5.1. Configuration Script 1.5.2. Ethernet Packet Generator Script
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices

1.2. Hardware and Software Requirements

Intel® uses the following hardware and software to test the reference design in a Linux system:

  • Intel® Quartus® Prime Pro Edition software version 20.4
  • For hardware testing:
    • Intel® Stratix® 10 GX L-Tile FPGA Development Board (1SG280LU2F50E2VG)
    • Micro USB cable
    • External Ethernet packet generator (for Avalon® streaming reverse loopback test only)
    • Ethernet Cat5e cable (for Avalon® streaming reverse loopback test only)
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