Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022
Public

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8.4. 3D LUT IP Registers

The 3D LUT IP allows run-time control and LUT programming via the CPU interface.
The register map provides access to the:
  • Build parameters such as LUT size and bits per color.
  • Control interface that allows you to enable or bypass the LUT. Also, it allows you to toggle buffers when you turn on Double buffered for the LUT.
  • RAM interface that allows programming of the LUT’s 8 sub-RAMs during run time and reading their contents if you turn on LUT read interface.
Table 38.  3D LUT IP register mapUnless stated, all the registers are 32-bit wide.
Register Name Byte Address Offset Access Description
vid_pid 0x000 RO Vendor ID and Product ID
version_number 0x004 RO Version number
- 0x008 RO Reserved
pixels_in_parallel 0x00C RO Video data format Number of pixels in parallel parameter
input_bps 0x010 RO Video data format Input bits per color sample parameter
output_bps 0x014 RO Video data format Output bits per color sample parameter
lut_alpha 0x018 RO LUT settings Output alpha channel parameter
lut_depth 0x01C RO LUT settings Bits per color parameter
lut_dimension 0x020 RO LUT settings Size parameter
lut_double_buffered 0x024 RO LUT settings Double buffered parameter
lut_cpu_readable 0x028 RO Control settings LUT read interface parameter
- 0x02C – 0x147 RO Reserved
Control 0x148 RW Control interface: enable and buffer select
0x14C – 0x17F RO Reserved
RAM n Control 0x180 + 0x10*n RW RAM n interface: address and write enable
0x184 + 0x10*n RW Reserved
RAM n Data Lower 0x188 + 0x10*n RW RAM n interface: data, lower 32 bits
RAM n Data Upper 0x18C + 0x10*n RW RAM n interface: data, upper 32 bits (if applicable)
Table 39.   vid_pid Register
Name Bits Description
PID 15:0 3D LUT Product ID: 0x0165
VID 31:16 Intel FPGA Vendor ID: 0x6AF7
Table 40.   version_number Register
Name Bits Description
Minor 15:0 Minor version number for this release of the 3D LUT IP
Major 31:16 Major version number for this release of the 3D LUT IP
Table 41.   pixels_in_parallel Register
Name Bits Description
Pixels in Parallel 31:0 Video data format Number of pixels in parallel parameter
Table 42.   input_bps Register
Name Bits Description
Input BPS 31:0 Video data format Input bits per color sample parameter
Table 43.   output_bps Register
Name Bits Description
Output BPS 31:0 Video data format Output bits per color sample parameter
Table 44.   lut_alpha Register
Name Bits Description
LUT alpha 31:0 LUT settings Output alpha channel parameter
Table 45.   lut_depth Register
Name Bits Description
LUT depth 31:0 LUT settings Bits per color parameter
Table 46.   lut_dimension Register
Name Bits Description
LUT dimension 31:0 LUT settings Size parameter
Table 47.   lut_double_buffered Register
Name Bits Description
LUT double buffered 31:0 LUT settings Double buffered parameter
Table 48.   lut_cpu_readable Register
Name Bits Description
LUT CPU readable 31:0 Control settings LUT read interface parameter
Table 49.  Control Register
Name Bits Description
Enable 0
  • 0: bypass
  • 1: enable LUT
Buffer select 1
  • 0: buffer 0
  • 1: buffer 1 (if Double buffered is enabled)
31:2 Reserved
Table 50.  RAM n Control Register
Name Bits Description
Address 16:0 RAM n address to write data to or read data from
27:17 Reserved
Write enable 28 Write enable (clears to 0 automatically)
31:29 Reserved
Table 51.  RAM n Data Lower Register
Name Bits Description
Data 31:0

LUT data, lower 32 bits

Write access: first write the new LUT entry data, then set the target address with the write enable asserted in RAM n Control

Read access: if you turn on LUT read interface, retrieve the data from RAM n at the address set in RAM n Control

Table 52.  RAM n Data Upper Register
Name Bits Description
Data 31:0

LUT data, upper 32 bits

Only present when the LUT data width is greater than 32, i.e.:

(lut_alpha + 3) * lut_depth > 32