AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Configuration Device Migration Guideline
1. Intel® FPGA Configuration Device Migration Guideline x
1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2. Software Migration Guidelines x
1.2.1. IP Core Compatibility 1.2.2. Programming File Compatibility 1.2.3. IP Core and Programming File Migration Guideline 1.2.4. Software Support for EPCQ-A Devices
1.2.3. IP Core and Programming File Migration Guideline x
1.2.3.1. IP Core Regeneration Guideline 1.2.3.2. Programming File Regeneration Guideline
1.3. Specification Comparison x
1.3.1. Operating Conditions 1.3.2. Timing Specifications 1.3.3. Operation Codes 1.3.4. Pin Information 1.3.5. Package Dimensions 1.3.6. Status Register
1.3.2. Timing Specifications x
1.3.2.1. Read Operation Timing 1.3.2.2. Write Operation Timing
1.3.4. Pin Information x
1.3.4.1. 8-pin SOIC Device Pin Information 1.3.4.2. 16-pin SOIC Device Pin Information
1.3.5. Package Dimensions x
1.3.5.1. 8-Pin SOIC Device Package Dimensions 1.3.5.2. 16-Pin SOIC Device Package Dimensions
1.3.6. Status Register x
1.3.6.1. Sector Protect
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices x
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme x
1.5.1.1. IBIS Simulation Example 1.5.1.2. Example for Adding the RC Network on DCLK 1.5.1.3. Example for Adding Buffer on the DCLK 1.5.1.4. Simulating the DCLK Signal at 100 MHz Operation 1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
1.5.1.2. Example for Adding the RC Network on DCLK x
1.5.1.2.1. Example for Simulating the DCLK Link 1.5.1.2.2. Example for Simulating the DATA Link 1.5.1.2.3. Simulation Results
1.5.1.3. Example for Adding Buffer on the DCLK x
1.5.1.3.1. Simulation Results
1. Intel® FPGA Configuration Device Migration Guideline

1.5.1.2.2. Example for Simulating the DATA Link

The following three simulation setups are essential to measure the minimum or maximum delay on the DATA signal.

Figure 14. Simulation Setup with the Default Maximum Load on the DATA Signal
  • The setup is used to measure the maximum delay on the DATA signal.
  • The maximum flash clock to output delay (tCLQV ) value in the EPCQ-A Serial Configuration Device Datasheet is based on 30pF loading.
Figure 15. Simulation Setup with the Default Minimum Load on the DATA Signal
  • The setup is used to measure the minimum delay on the DATA signal.
  • The minimum flash clock to output delay (tCLQX ) value in the EPCQ-A Serial Configuration Device Datasheet is based on 0pF loading.
Figure 16. Simulation Setup with the Actual System Load on the DATA Signal
Figure 17. Maximum DATA Delay

The maximum DATA delay is calculated by substituting the delay measured between E and C in the simulation into the following equation.

Maximum DATA delay = tCLQV + (delay measurement E – delay measurement C)

Maximum DATA delay = 6ns – 2.343ns

Maximum DATA delay = 3.657ns

The results clearly show that the maximum DATA delay could be smaller depending on the actual system loading which helps to improve the FPGA setup time slack. Using the tCLQV value defined in the EPCQ-A Serial Configuration Device Datasheet is too pessimistic in the setup time analysis.

Figure 18. Minimum DATA Delay

The minimum DATA delay is calculated by substituting the delay measured between E and D in the simulation into the following equation.

Minimum DATA delay = tCLQX + (delay measurement E – delay measurement D)

Minimum DATA delay = 1.5ns + 0.542ns

Minimum DATA delay = 2.042ns

The results clearly show that the minimum DATA delay could be larger depending on the actual system loading. Using the tCLQX value defined in the EPCQ-A Serial Configuration Device Datasheet is too pessimistic for the hold time analysis.

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