AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Configuration Device Migration Guideline
1. Intel® FPGA Configuration Device Migration Guideline x
1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2. Software Migration Guidelines x
1.2.1. IP Core Compatibility 1.2.2. Programming File Compatibility 1.2.3. IP Core and Programming File Migration Guideline 1.2.4. Software Support for EPCQ-A Devices
1.2.3. IP Core and Programming File Migration Guideline x
1.2.3.1. IP Core Regeneration Guideline 1.2.3.2. Programming File Regeneration Guideline
1.3. Specification Comparison x
1.3.1. Operating Conditions 1.3.2. Timing Specifications 1.3.3. Operation Codes 1.3.4. Pin Information 1.3.5. Package Dimensions 1.3.6. Status Register
1.3.2. Timing Specifications x
1.3.2.1. Read Operation Timing 1.3.2.2. Write Operation Timing
1.3.4. Pin Information x
1.3.4.1. 8-pin SOIC Device Pin Information 1.3.4.2. 16-pin SOIC Device Pin Information
1.3.5. Package Dimensions x
1.3.5.1. 8-Pin SOIC Device Package Dimensions 1.3.5.2. 16-Pin SOIC Device Package Dimensions
1.3.6. Status Register x
1.3.6.1. Sector Protect
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices x
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme x
1.5.1.1. IBIS Simulation Example 1.5.1.2. Example for Adding the RC Network on DCLK 1.5.1.3. Example for Adding Buffer on the DCLK 1.5.1.4. Simulating the DCLK Signal at 100 MHz Operation 1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
1.5.1.2. Example for Adding the RC Network on DCLK x
1.5.1.2.1. Example for Simulating the DCLK Link 1.5.1.2.2. Example for Simulating the DATA Link 1.5.1.2.3. Simulation Results
1.5.1.3. Example for Adding Buffer on the DCLK x
1.5.1.3.1. Simulation Results
1. Intel® FPGA Configuration Device Migration Guideline

1.5.1.2.3. Simulation Results

The following table shows the minimum and maximum delays on the DCLK and DATA links can be obtained accurately via the IBIS simulation.

Table 23.  Minimum and Maximum Delays on the DCLK and DATA Links
Signal IC Corner Total Delay Measured via IBIS Simulation at VCC/2 (ns)27 Notes
DCLK Fast/Strong 2.514 Minimum DCLK delay
DCLK Slow/Weak 3.886 Maximum DCLK delay
DATA Fast/Strong 2.042 Minimum DATA delay
DATA Slow/Weak 3.657 Maximum DATA delay

Ultimately, the data setup time slack and the data hold time slack can be obtained by substituting the delay obtained from the IBIS simulation in the following equations.

Assumption for the system setup:

  • DCLK frequency: 50MHz (period 20ns)
  • Cyclone® V AS timing specifications:
    • Minimum tDSU : 1.5ns
    • Minimum tDH : 2.9ns

This equation shows the data setup time slack calculation.

Data setup time slack = tDCLK – tDSU – (maximum DCLK delay + maximum DATA delay)

Data setup time slack = 20ns – 1.5ns – (3.886ns + 3.657ns)

Data setup time slack = 10.957ns

This equation shows the data hold time slack calculation.

Data hold time slack = (Minimum DCLK delay + minimum DATA delay) – tDH

Data hold time slack = (2.514ns + 2.042ns) – 2.9ns

Data hold time slack = 1.656ns

The DCLK signal quality is good with the extra RC network as shown in the simulation waveform below. The DCLK signal is simulated using 50 Mbps clock pattern.

Figure 19. Simulating the DCLK Signal at 50 Mbps Operation

By adding the recommended RC network, the DCLK and DATA trace lengths can be designed to as short as possible and are able to meet the minimum data setup or hold time required by the Cyclone® V FPGA.

A smaller maximum DATA delay can be obtained via the simulation technique. The FPGA AS configuration data setup time slack can be improved with the simulation value compared to the flash datasheet specifications.

A larger minimum DATA delay can be obtained via the simulation technique. The FPGA AS configuration data hold time slack can be improved with simulation value compared to the flash datasheet specifications.

27 The data listed is based on the manual measurement from the simulation waveform.
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