AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Configuration Device Migration Guideline
1. Intel® FPGA Configuration Device Migration Guideline x
1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2. Software Migration Guidelines x
1.2.1. IP Core Compatibility 1.2.2. Programming File Compatibility 1.2.3. IP Core and Programming File Migration Guideline 1.2.4. Software Support for EPCQ-A Devices
1.2.3. IP Core and Programming File Migration Guideline x
1.2.3.1. IP Core Regeneration Guideline 1.2.3.2. Programming File Regeneration Guideline
1.3. Specification Comparison x
1.3.1. Operating Conditions 1.3.2. Timing Specifications 1.3.3. Operation Codes 1.3.4. Pin Information 1.3.5. Package Dimensions 1.3.6. Status Register
1.3.2. Timing Specifications x
1.3.2.1. Read Operation Timing 1.3.2.2. Write Operation Timing
1.3.4. Pin Information x
1.3.4.1. 8-pin SOIC Device Pin Information 1.3.4.2. 16-pin SOIC Device Pin Information
1.3.5. Package Dimensions x
1.3.5.1. 8-Pin SOIC Device Package Dimensions 1.3.5.2. 16-Pin SOIC Device Package Dimensions
1.3.6. Status Register x
1.3.6.1. Sector Protect
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices x
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme x
1.5.1.1. IBIS Simulation Example 1.5.1.2. Example for Adding the RC Network on DCLK 1.5.1.3. Example for Adding Buffer on the DCLK 1.5.1.4. Simulating the DCLK Signal at 100 MHz Operation 1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
1.5.1.2. Example for Adding the RC Network on DCLK x
1.5.1.2.1. Example for Simulating the DCLK Link 1.5.1.2.2. Example for Simulating the DATA Link 1.5.1.2.3. Simulation Results
1.5.1.3. Example for Adding Buffer on the DCLK x
1.5.1.3.1. Simulation Results
1. Intel® FPGA Configuration Device Migration Guideline

1.3.1. Operating Conditions

Table 5.  EPCS, EPCQ and EPCQ-A Devices Operating Conditions
Parameter Condition Symbol Min Max Unit
EPCS EPCQ EPCQ-A EPCS EPCQ EPCQ-A
Supply voltage The maximum VCC rise time is 100 ms. VCC 2.7 3.6 V
Operating temperature For industrial use TA -40 85 °C
High-level input voltage — VIH 0.7 x VCC 10 11 VCC + 0.4 V
Low-level input voltage — VIL -0.5 0.3 x VCC V
High-level output voltage IOH =-100µA VOH VCC - 0.2 — V
Low-level output voltage IOL =100µA VOL — 0.2 or 0.412 V
10 The FPGA 2.5V I/O VOH level is insufficient to achieve EPCQ or EPCQ-A VIH threshold across entire voltage range.
11 The minimum VOH for 3V or 3.3V LVTTL is 2.4V in the Intel® FPGA device. This specification is based on the worst condition. Since the input current of EPCQ and EPCQ-A is small enough, the VOH of Intel® FPGA device does not violate the minimum VIH of EPCQ and EPCQ-A in the usual usage. Intel® recommends that you perform simulation using the IBIS model to ensure the required specifications are achieved.
12 0.2 V for EPCQ16A, EPCQ32A, EPCQ64A, and EPCQ128A. 0.4 V is for EPCQ4A
Level Two Title