Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

Download PDF
ID 683367
Date 7/01/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices 2. Setting Up the Ethernet Link Inspector 3. Functional Description 4. Ethernet Link Inspector User Guide Archives 5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Supported IP Cores and Devices
1.1. Features x
1.1.1. Link Monitor 1.1.2. Link Analysis
2. Setting Up the Ethernet Link Inspector x
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Link Inspector
2.1. System Requirements and Prerequisites x
2.1.1. System Requirements 2.1.2. Enabling Your Design For the Link Monitor
2.2. Running the Ethernet Link Inspector x
2.2.1. Running the Link Monitor 2.2.2. Running the Link Analysis
2.2.2. Running the Link Analysis x
2.2.2.1. Creating and Capturing Signal Tap File and Exporting Signal Tap Database as CSV File
3. Functional Description x
3.1. Link Monitor Module 3.2. Link Analysis Module
3.1. Link Monitor Module x
3.1.1. Link Monitor Tabs and Settings
3.2. Link Analysis Module x
3.2.1. Sequencer State Machine 3.2.2. Link Analysis Tabs and Settings
3.2.2. Link Analysis Tabs and Settings x
3.2.2.1. Sequencer State Machine Tab 3.2.2.2. Auto Neg Tab 3.2.2.3. Link Training Tab 3.2.2.4. Data Mode Tab 3.2.2.5. Help Tab
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices
2. Setting Up the Ethernet Link Inspector
3. Functional Description
4. Ethernet Link Inspector User Guide Archives
5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

2.1.2. Enabling Your Design For the Link Monitor

To enable the use of Link Monitor, your design must instantiate JTAG to Avalon® Master Bridge. The availability of the JTAG to Avalon® Master bridge in the Intel® Stratix® 10 Ethernet IP cores is shown in the following table.

Table 2.  Availability of JTAG to Avalon® Master Bridge in Intel® Stratix® 10 Ethernet IP Cores
Device IP Core Data Rate (Gbps) IP Type Design Example 2 Standalone IP 3
Intel® Stratix® 10 L-Tile 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP 10 Soft Yes Yes
25G Ethernet Intel® FPGA IP 25 Soft Yes N/A
Low Latency 40G Ethernet Intel® FPGA IP 40 Soft Yes Yes
Low Latency 100G Ethernet Intel® FPGA IP 100 Soft Yes Yes
Intel® Stratix® 10 H-Tile 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP 10 Soft Yes Yes
25G Ethernet Intel® FPGA IP 25 Soft Yes N/A
Low Latency 40G Ethernet Intel® FPGA IP 40 Soft Yes Yes
Low Latency 100G Ethernet Intel® FPGA IP 100 Soft Yes Yes
H-Tile Hard IP for Ethernet Intel® FPGA IP 50 Hard Yes Yes
100 Hard Yes Yes
Intel® Stratix® 10 E-Tile E-Tile Hard IP for Ethernet Intel® FPGA IP 10 Hard Yes Yes
25 Hard Yes Yes
100

(25Gx4-NRZ)

 Hard Yes Yes
100

(50Gx2-PAM4)

 Hard Yes Yes
Related Information
2 Design examples generated in Intel® Quartus® Prime Pro Edition software are instantiated with JTAG to Avalon® Master Bridge. These design examples also include Ethernet Packet Generators that can be controlled using the Link Monitor.
3 Supported standalone IPs provide an option called Enable JTAG to Avalon® Master Bridge in the respective IP Parameter Editor GUI in Intel® Quartus® Prime Pro Edition software. The selection of this option automatically includes JTAG to Avalon® Master Bridge during IP generation. This JTAG to Avalon® Master Bridge do not provide access to Packet Generators, which is originally part of design example. For non-supported standalone IPs, the JTAG to Avalon® Master Bridge has to be manually instantiated from the IP Catalog. Refer to respective IP design example RTL and user guides for more details on IP connections.
Level Two Title