Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

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ID 683367
Date 7/01/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices 2. Setting Up the Ethernet Link Inspector 3. Functional Description 4. Ethernet Link Inspector User Guide Archives 5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Supported IP Cores and Devices
1.1. Features x
1.1.1. Link Monitor 1.1.2. Link Analysis
2. Setting Up the Ethernet Link Inspector x
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Link Inspector
2.1. System Requirements and Prerequisites x
2.1.1. System Requirements 2.1.2. Enabling Your Design For the Link Monitor
2.2. Running the Ethernet Link Inspector x
2.2.1. Running the Link Monitor 2.2.2. Running the Link Analysis
2.2.2. Running the Link Analysis x
2.2.2.1. Creating and Capturing Signal Tap File and Exporting Signal Tap Database as CSV File
3. Functional Description x
3.1. Link Monitor Module 3.2. Link Analysis Module
3.1. Link Monitor Module x
3.1.1. Link Monitor Tabs and Settings
3.2. Link Analysis Module x
3.2.1. Sequencer State Machine 3.2.2. Link Analysis Tabs and Settings
3.2.2. Link Analysis Tabs and Settings x
3.2.2.1. Sequencer State Machine Tab 3.2.2.2. Auto Neg Tab 3.2.2.3. Link Training Tab 3.2.2.4. Data Mode Tab 3.2.2.5. Help Tab
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices
2. Setting Up the Ethernet Link Inspector
3. Functional Description
4. Ethernet Link Inspector User Guide Archives
5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

3.2.1. Sequencer State Machine

The Ethernet IP cores for Intel® Stratix® 10 devices implement an internal state machine called Sequencer State Machine (SSM) that represents the Ethernet IP link bring-up. At any point of time, the device should be in one of SSM states.

Figure 6. Flowchart of SSM StatesThis figure shows the various states of SSM and how these states are mapped to the operational modes.
Table 4.  SSM State Descriptions
SSM State Description
SSM_ENABLE

The first state used for Sequencer State Machine (SSM) initialization. This should be the first state of device after a power cycle or a reset. If Auto Negotiation (AN) and Link Training (LT) are enabled, the local device moves to the SSM_RC_AN state after this state is completes.

SSM_RC_AN Indicates the reconfiguration of PHY for Auto Negotiation operation.
SSM_AN_ABL After the completion of SSM_RC_AN state, the local device goes into the SSM_AN_ABL state. In this state, the transmitter of the local device is disabled (i.e., no transitions) so that the Ethernet IP link goes down and the Ethernet IP link partner also goes back to Auto Negotiation. Even without any Ethernet IP link partners connected, the local device should complete this state and move to the next state i.e., SSM_AN_CHK. The local device spends an approximate time of 60 to 75 milliseconds (ms) in this state. At the end of this state, the local device starts sending AN Base Page to the remote device.
SSM_AN_CHK

Once the local device starts sending AN base page, it moves to the state SSM_AN_CHK. The rest of the AN happens in this state. The following are major AN events that happen in this state:

  1. Waiting for AN base Page from Remote Device
  2. Waiting for an ACK from Remote Device
  3. Sending an ACK to Remote Device
  4. Doing NEXT PAGE communication (if any)
  5. Asserting the an_done signal

Various events during AN are further categorized into a separate state machine called AN Arbiter State Machine. Refer to Auto Neg Tab for more details.

SSM_RC_LT Indicates the reconfiguration of PHY for LT operation.
SSM_LT_CHK

After completion of SSM_RC_LT, device goes into SSM_LT_CHK state. This state includes the LT packet communication between the two devices, local and remote. At the end of this state, both devices should have completed LT and acknowledge each other upon completion.

SSM_RC_10G 4

SSM_RC_DAT 5

Indicates that the reconfiguration of PHY for:
  • 10G/10GFEC mode for 10GBASE-KR operation.
  • 40G/40GFEC mode for 40GBASE-KR4 operation.
  • 50G and 100G modes for H-tile Hard and 100GBASE-KR4 Low Latency operation.
SSM_10G_CHK 4

SSM_LNK_CHK 5

After the completion of the SSM_RC_10G/SSM_RC_DAT state, the local device goes into the SSM_10G_CHK/SSM_LNK_CHK state. In this state, the local device tries to achieve lock on the received Ethernet packets. The following status signals shows the lock status:

  1. 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP core: rx_data_ready
  2. For Low Latency 40G Intel® FPGA IP core: rpcs_deskew_lock
  3. For Intel® Stratix® 10 H-Tile Hard 50G and 100G IP cores: o_rx_am_lock
  4. For Low Latency 100G Intel® FPGA IP core: deskew_lock

The local device will move to the next state called SSM_LNK_RDY when the lock conditions are met.

The local device can only remain in this state if the total time, starting from SSM_RC_LT, does not exceed 500 ms. If the total time exceeds 500 ms and the lock conditions are still not met, the local device goes back to SSM_ENABLE state and redo the AN and LT.

SSM_LNK_RDY Indicates that the local device has successfully locked on to the received Ethernet packets and processed them accordingly. The local device is expected to be in this state during the entire exchange of Ethernet packets unless it losses lock (rx_data_ready or rx_is_lockedtodata). If the local device losses lock, it goes to the next SSM state called SSM_LR_WAIT.
SSM_LR_WAIT

The Ethernet IP link goes into SSM_LR_WAIT state if any of the following lock status signals goes low during SSM_LNK_RDY state:

  1. For 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP core: rx_data_ready or rx_is_lockedtodata
  2. For Low Latency 40G Intel® FPGA IP core: rpcs_deskew_locked or rx_is_lockedtodata
  3. For Intel® Stratix® 10 H-Tile Hard 50G and 100G IP cores: o_rx_am_lock or rx_is_lockedtodata
  4. For Low Latency 100G Intel® FPGA IP core: deskew_locked or rx_is_lockedtodata

For example, the local device wait for maximum of 1000 clock cycles to check if the lock conditions are met. If lock conditions are not met within 1000 clock cycles, the link goes back into SSM_ENABLE state. If the lock conditions are met any time before the 1000 clock cycles, the link goes back to SSM_LINK_RDY state.

4 SSM state for 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP and Low Latency 40G Ethernet Intel® FPGA IP cores.
5 SSM state for Intel® Stratix® 10 H-Tile Hard 50G and 100G IP cores and Low Latency 100G Intel® FPGA IP core.
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