Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 10/01/2021
Public

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Document Table of Contents

2.1.1. Byte Enable Controls

Table 2.  Byte Enable Controls in ×10 Data Width (MLAB)
Byte Enable [1:0] Data Bits Written
11 (default) [9:5] [4:0]
10 [9:5] N/A
01 N/A [4:0]
00 N/A N/A
Table 3.  Byte Enable Controls in ×20 Data Width (M20K)
Byte Enable [1:0] Data Bits Written
11 (default) [19:10] [9:0]
10 [19:10] N/A
01 N/A [9:0]
00 N/A N/A
Table 4.  Byte Enable Controls in ×40 Data Width (M20K)
Byte Enable [3:0] Data Bits Written
1111 (default) [39:30] [29:20] [19:10] [9:0]
1110 [39:30] [29:20] [19:10] N/A
1101 [39:30] [29:20] N/A [9:0]
1100 [39:30] [29:20] N/A N/A
1011 [39:30] N/A [19:10] [9:0]
1010 [39:30] N/A [19:10] N/A
1001 [39:30] N/A N/A [9:0]
1000 [39:30] N/A N/A N/A
0111 N/A [29:20] [19:10] [9:0]
0110 N/A [29:20] [19:10] N/A
0101 N/A [29:20] N/A [9:0]
0100 N/A [29:20] N/A N/A
0011 N/A N/A [19:10] [9:0]
0010 N/A N/A [19:10] N/A
0001 N/A N/A N/A [9:0]
0000 N/A N/A N/A N/A