Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 10/01/2021
Public

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2.7. Freeze Logic

The freeze logic feature specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region.
This feature is applicable only to the RAM modes:
  • Single-port RAM
  • Dual-port RAM
  • Quad-port RAM

You have the option to turn on Implement clock-enable circuitry for use in a partial reconfiguration to enable the freeze logic feature in the parameter editors of the RAM IPs.