AN 720: Simulating the ASMI Block in Your Design

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ID 683464
Date 7/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Simulating the ASMI Block in Your Design
1. Simulating the ASMI Block in Your Design x
1.1. Supported Devices 1.2. Overview 1.3. Simulating the ASMI Block in Your Design 1.4. Document Revision History for AN 720: Simulating the ASMI Block in Your Design
1.2. Overview x
1.2.1. Block Diagrams for ASMI Block 1.2.2. Signals for ASMI Block 1.2.3. WYSIWYG for ASMI Block
1.3. Simulating the ASMI Block in Your Design x
1.3.1. Example: Simulating the ASMI Block in a Stratix® V Device Using EPCQ Flash 1.3.2. Example: Simulating the ASMI Block in a Stratix® V Device Using Third-Party Flash Devices
1. Simulating the ASMI Block in Your Design

1.2.2. Signals for ASMI Block

This table lists the ASMI block signals.
Table 1.  Signals for ASMI Block
Signal Direction Width (bits) Description
dclk Input 1 Clock signal from your FPGA design to the external DCLK pin through the ASMI hard logic.
sce Input 3 Chip select signal from your FPGA design to the external nCSO pin through the ASMI hard logic.
oe Input 1 Active-low signal to enable DCLK and nCSO pins to reach the flash. The DCLK and nCSO are fixed to high when you set this signal to high, blocking the connection between FPGA and flash.
data0out Input of the ASMI block, which outputs the data from your FPGA design to the AS data pin 4

Control signal from your FPGA design to the AS data pin for sending data into the serial configuration device.

If you want to connect your Intel® Arria® 10, Arria® V, Arria® V GZ, Cyclone® V, or Stratix® V device to the EPCS device, Altera recommends setting the data out ports to the following:

  • data0out = FPGA design data to the EPCS through the AS_DATA0 pin.
  • data1out = 1'b0
  • data2out = 1'b1
  • data3out = 1'b1
data1out
data2out
data3out
data0oe Input 4

Controls data pin either as input or output because the dedicated pins for active serial data is bidirectional.

To set the AS data pin as input, set the desired data pin oe to 0.

To set the AS data pin as output, set the desired data pin oe to 1.

If you want to connect your Intel® Arria® 10, Arria® V, Arria® V GZ, Cyclone® V or Stratix® V device to the EPCS device, then set the data pin oe to the following:

  • data0oe = 1'b1
  • data1oe = 1'b0
  • data2oe = 1'b1
  • data3oe = 1'b1
data1oe
data2oe
data3oe
data0in Output of the ASMI block, which receives input from the AS data pin and outputs to your FPGA design 4

Signal from the AS data pin to your FPGA design.

If you want to connect your Intel® Arria® 10, Arria® V, Arria® V GZ, Cyclone® V or Stratix® V device to the EPCS device, then set the data in pin to the following:

  • data0in = don't care
  • data1in = EPCS device data to your FPGA design through the AS_DATA1 pin.
  • data2in = don't care
  • data3in = don't care
data1in
data2in
data3in
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