Stratix® 10 10GBASE-KR PHY IP Core User Guide

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ID 683500
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Stratix® 10 10GBASE-KR PHY IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Stratix® 10 10GBASE-KR PHY Registers 6. Interface Signals 7. Design Example 8. Supported Tools A. Difference between Stratix® 10 and Arria® 10 IP Variants B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
1. About the Stratix® 10 10GBASE-KR PHY IP Core x
1.1. Stratix® 10 10GBASE-KR PHY IP Core Supported Features 1.2. Device Family Support 1.3. IP Core Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Integrating Your IP Core in Your Design 2.6. Stratix® 10 10GBASE-KR IP Core Testbench 2.7. Compiling the Full design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the fPLL 2.5.4. Adding the Stratix® 10 Transceiver PHY Reset Controller 2.5.5. Placement Settings for the Stratix® 10 10GBASE-KR PHY IP Core
5. Stratix® 10 10GBASE-KR PHY Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Data Interface Signals 6.3. Serial Data Signals 6.4. Avalon® -MM Interface Signals 6.5. Transceiver Reconfiguration Signals 6.6. Control and Status Signals
6.2. Data Interface Signals x
6.2.1. XGMII Mapping to Standard SDR XGMII Data
7. Design Example x
7.1. Quick Start Guide 7.2. Design Example Description
7.1. Quick Start Guide x
7.1.1. Design Example Directory Structure 7.1.2. Hardware Design Example Components 7.1.3. Simulation Design Example Components 7.1.4. Generating the Design Example 7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench 7.1.6. Compiling and Configuring the Design Example in Hardware 7.1.7. Testing the Hardware Design Example
7.2. Design Example Description x
7.2.1. Hardware and Software Requirements 7.2.2. Design Example Behavior 7.2.3. Design Example Interface Signals 7.2.4. Stratix® 10 10GBASE-KR PHY Design Example Registers
8. Supported Tools x
8.1. Ethernet Toolkit Overview
8.1. Ethernet Toolkit Overview x
8.1.1. Features
1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide

2.5.2. Adding the Transceiver PLL

Stratix® 10 10GBASE-KR PHY IP core requires an external PLL to drive the TX transceiver serial clock, in order to compile and to function correctly in hardware. In many cases, the same PLL can be shared with other transceivers in your design.

The TX transceiver PLL is instantiated with an Intel FPGA ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the Stratix® 10 10GBASE-KR PHY IP core.

You can use the IP Catalog to create a transceiver PLL.
  • Select Stratix 10 L-Tile/H-Tile Transceiver ATX PLL.
  • In the parameter editor, set the following parameter values:
    • PLL output frequency to 5156.25 MHz
    • PLL auto mode reference clock frequency (integer) to 644.53125 MHz or 322.265625 MHz

You must connect the tx_serial_clk input pin of the Stratix® 10 10GBASE-KR IP core PHY link to the output port of the ATX PLL.

Level Two Title