Stratix® 10 10GBASE-KR PHY IP Core User Guide

Download PDF
ID 683500
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Stratix® 10 10GBASE-KR PHY IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Stratix® 10 10GBASE-KR PHY Registers 6. Interface Signals 7. Design Example 8. Supported Tools A. Difference between Stratix® 10 and Arria® 10 IP Variants B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
1. About the Stratix® 10 10GBASE-KR PHY IP Core x
1.1. Stratix® 10 10GBASE-KR PHY IP Core Supported Features 1.2. Device Family Support 1.3. IP Core Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Integrating Your IP Core in Your Design 2.6. Stratix® 10 10GBASE-KR IP Core Testbench 2.7. Compiling the Full design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the fPLL 2.5.4. Adding the Stratix® 10 Transceiver PHY Reset Controller 2.5.5. Placement Settings for the Stratix® 10 10GBASE-KR PHY IP Core
5. Stratix® 10 10GBASE-KR PHY Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Data Interface Signals 6.3. Serial Data Signals 6.4. Avalon® -MM Interface Signals 6.5. Transceiver Reconfiguration Signals 6.6. Control and Status Signals
6.2. Data Interface Signals x
6.2.1. XGMII Mapping to Standard SDR XGMII Data
7. Design Example x
7.1. Quick Start Guide 7.2. Design Example Description
7.1. Quick Start Guide x
7.1.1. Design Example Directory Structure 7.1.2. Hardware Design Example Components 7.1.3. Simulation Design Example Components 7.1.4. Generating the Design Example 7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench 7.1.6. Compiling and Configuring the Design Example in Hardware 7.1.7. Testing the Hardware Design Example
7.2. Design Example Description x
7.2.1. Hardware and Software Requirements 7.2.2. Design Example Behavior 7.2.3. Design Example Interface Signals 7.2.4. Stratix® 10 10GBASE-KR PHY Design Example Registers
8. Supported Tools x
8.1. Ethernet Toolkit Overview
8.1. Ethernet Toolkit Overview x
8.1.1. Features
1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide

6.2.1. XGMII Mapping to Standard SDR XGMII Data

Table 13.  TX XGMII Mapping to Standard SDR XGMII InterfaceThe 72-bit TX XGMII data bus format is different than the standard SDR XGMII interface. This table shows the mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name SDR XGMII Signal Name Description
xgmii_tx_dc[7:0] xgmii_sdr_data[7:0] Lane 0 data
xgmii_tx_dc[8] xgmii_sdr_ctrl[0] Lane 0 control
xgmii_tx_dc[16:9] xgmii_sdr_data[15:8] Lane 1 data
xgmii_tx_dc[17] xgmii_sdr_ctrl[1] Lane 1 control
xgmii_tx_dc[25:18] xgmii_sdr_data[23:16] Lane 2 data
xgmii_tx_dc[26] xgmii_sdr_ctrl[2] Lane 2 control
xgmii_tx_dc[34:27] xgmii_sdr_data[31:24] Lane 3 data
xgmii_tx_dc[35] xgmii_sdr_ctrl[3] Lane 3 control
xgmii_tx_dc[43:36] xgmii_sdr_data[39:32] Lane 4 data
xgmii_tx_dc[44] xgmii_sdr_ctrl[4] Lane 4 control
xgmii_tx_dc[52:45] xgmii_sdr_data[47:40] Lane 5 data
xgmii_tx_dc[53] xgmii_sdr_ctrl[5] Lane 5 control
xgmii_tx_dc[61:54] xgmii_sdr_data[55:48] Lane 6 data
xgmii_tx_dc[62] xgmii_sdr_ctrl[6] Lane 6 control
xgmii_tx_dc[70:63] xgmii_sdr_data[63:56] Lane 7 data
xgmii_tx_dc[71] xgmii_sdr_ctrl[7] Lane 7 control
Table 14.   RX XGMII Mapping to Standard SDR XGMII Interface The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name XGMII Signal Name Description
xgmii_rx_dc[7:0] xgmii_sdr_data[7:0] Lane 0 data
xgmii_rx_dc[8] xgmii_sdr_ctrl[0] Lane 0 control
xgmii_rx_dc[16:9] xgmii_sdr_data[15:8] Lane 1 data
xgmii_rx_dc[17] xgmii_sdr_ctrl[1] Lane 1 control
xgmii_rx_dc[25:18] xgmii_sdr_data[23:16] Lane 2 data
xgmii_rx_dc[26] xgmii_sdr_ctrl[2] Lane 2 control
xgmii_rx_dc[34:27] xgmii_sdr_data[31:24] Lane 3 data
xgmii_rx_dc[35] xgmii_sdr_ctrl[3] Lane 3 control
xgmii_rx_dc[43:36] xgmii_sdr_data[39:32] Lane 4 data
xgmii_rx_dc[44] xgmii_sdr_ctrl[4] Lane 4 control
xgmii_rx_dc[52:45] xgmii_sdr_data[47:40] Lane 5 data
xgmii_rx_dc[53] xgmii_sdr_ctrl[5] Lane 5 control
xgmii_rx_dc[61:54] xgmii_sdr_data[55:48] Lane 6 data
xgmii_rx_dc[62] xgmii_sdr_ctrl[6] Lane 6 control
xgmii_rx_dc[70:63] xgmii_sdr_data[63:56] Lane 7 data
xgmii_rx_dc[71] xgmii_sdr_ctrl[7] Lane 7 control
Level Two Title