Stratix® 10 10GBASE-KR PHY IP Core User Guide

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ID 683500
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Stratix® 10 10GBASE-KR PHY IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Stratix® 10 10GBASE-KR PHY Registers 6. Interface Signals 7. Design Example 8. Supported Tools A. Difference between Stratix® 10 and Arria® 10 IP Variants B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
1. About the Stratix® 10 10GBASE-KR PHY IP Core x
1.1. Stratix® 10 10GBASE-KR PHY IP Core Supported Features 1.2. Device Family Support 1.3. IP Core Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Integrating Your IP Core in Your Design 2.6. Stratix® 10 10GBASE-KR IP Core Testbench 2.7. Compiling the Full design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the fPLL 2.5.4. Adding the Stratix® 10 Transceiver PHY Reset Controller 2.5.5. Placement Settings for the Stratix® 10 10GBASE-KR PHY IP Core
5. Stratix® 10 10GBASE-KR PHY Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Data Interface Signals 6.3. Serial Data Signals 6.4. Avalon® -MM Interface Signals 6.5. Transceiver Reconfiguration Signals 6.6. Control and Status Signals
6.2. Data Interface Signals x
6.2.1. XGMII Mapping to Standard SDR XGMII Data
7. Design Example x
7.1. Quick Start Guide 7.2. Design Example Description
7.1. Quick Start Guide x
7.1.1. Design Example Directory Structure 7.1.2. Hardware Design Example Components 7.1.3. Simulation Design Example Components 7.1.4. Generating the Design Example 7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench 7.1.6. Compiling and Configuring the Design Example in Hardware 7.1.7. Testing the Hardware Design Example
7.2. Design Example Description x
7.2.1. Hardware and Software Requirements 7.2.2. Design Example Behavior 7.2.3. Design Example Interface Signals 7.2.4. Stratix® 10 10GBASE-KR PHY Design Example Registers
8. Supported Tools x
8.1. Ethernet Toolkit Overview
8.1. Ethernet Toolkit Overview x
8.1.1. Features
1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide

6.1. Clock and Reset Signals

Table 11.  Clock and Reset Signals
Signal Name Direction Description
Clock signals
tx_serial_clk_10g Input High speed clock from the 10G PLL to drive 10G PHY TX PMA. The frequency of this clock is 5.15625 GHz.
rx_cdr_ref_clk_10g Input 10G PHY RX PLL reference clock. This clock frequency can be 644.53125 MHz or 322.2656 MHz.
xgmii_tx_clk Input Clock for single data rate (SDR) XGMII TX interface to the MAC. This clock can be connected to the tx_pma_div_clkout. The frequency is 156.25 MHz. The frequencies are the same whether or not you enable FEC.
xgmii_rx_clk Input Clock for SDR XGMII RX interface to the MAC. This clock can be connected to the tx_pma_div_clkout. The frequency is 156.25 MHz. The frequencies are the same whether or not you enable FEC.
rx_clkout Output XGMII RX clock for the RX parallel data source interface. This clock frequency is 257.81 in 10G mode, and 161.13 MHz with FEC enabled.

rx_clkout is a recovered clock. Therefore, the modules using this clock should be held in reset until rx_is_lockedtodata is high for enough time to indicate a stable clock. For more information, refer to Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide.

tx_clkout Output XGMII/GMII TX clock for the TX parallel data source interface. This clock frequency is 257.81 MHz in 10G mode, and 161.13 MHz with FEC enabled.
mgmt_clk Input

The clock signal that controls the Avalon-MM PHY management interface. This clock is used for both the PHY management interface and transceiver reconfiguration. You must restrict the frequency to a rate between 100 MHz and 161 MHz (inclusive) to meet the specification for the transceiver reconfiguration clock.

rx_div_clk Output

The divided 33 clock from the received data. It drives the AN and LT logic and is sourced from the Native PHY rx_pma_div_clkout port.

The frequency is 156.25 MHz for 10G. This clock is from the PMA and it is not to be used to clock the 10G RX datapath. Use tx_clkout or xgmii_rx_clk for 10G TX datapath clocking.

tx_pma_div_clkout Output The divided 33 clock from the TX serializer. You can use this clock for the for xgmii_tx_clk or xgmii_rx_clk. The frequency is 156.25 MHz for 10G. The frequencies are the same whether or not you enable FEC.
rx_pma_div_clkout Output The divided 33 clock from CDR recovered clock. The frequency is 156.25 MHz for 10G. The frequencies are the same whether or not you enable FEC. This clock is not used for clocking the 10G RX datapath.

rx_pma_div_clkout is a recovered clock. Therefore, the modules using this clock should be held in reset untilrx_is_lockedtodata is high for enough time to indicate a stable clock. For more information, refer to Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide .

Reset signals
mgmt_clk_reset Input

Resets the PHY management interface. This asynchronous signal

is active high and level sensitive.
tx_analogreset Input Resets the analog TX portion of the transceiver PHY. Synchronous to mgmt_clk.
tx_digitalreset Input Resets the digital TX portion of the transceiver PHY. Synchronous to mgmt_clk.
rx_analogreset Input Resets the analog RX portion of the transceiver PHY. Synchronous to mgmt_clk.
rx_digitalreset Input Resets the digital RX portion of the transceiver PHY. Synchronous to mgmt_clk
tx_analogreset_stat Output When asserted, the reset sequence for TX PMA has begun. When deasserted, the reset sequence has finished.

Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.

tx_digitalreset_stat Output When asserted, the reset sequence for TX PCS has begun. When deasserted, the reset sequence has finished.

Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.

rx_analogreset_stat Output When asserted, the reset sequence for RX PMA has begun. When deasserted, the reset sequence has finished.

Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.

rx_digitalreset_stat Output When asserted, the reset sequence for RX PCS has begun. When deasserted, the reset sequence has finished.

Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.

usr_seq_reset Input Resets the sequencer. Initiates a PCS reconfiguration, and may restart AN, LT or both if these modes are enabled. Synchronous to mgmt_clk.
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