AN 456: PCI Express High Performance Reference Design

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ID 683541
Date 12/12/2018
Public
Document Table of Contents
Document Table of Contents x
1. PCI Express High Performance Reference Design
1. PCI Express High Performance Reference Design x
1.1. Understanding Throughput in PCI Express 1.2. Deliverables Included with the Reference Design 1.3. Reference Design Functional Description 1.4. Hardware Requirements 1.5. Software Requirements 1.6. Software Installation 1.7. Hardware Installation 1.8. Running the Software Application 1.9. Additional Chaining DMA Commands 1.10. Using SignalTap II 1.11. Performance Benchmarking Results 1.12. Document Revision History
1.1. Understanding Throughput in PCI Express x
1.1.1. Protocol Overhead 1.1.2. Throughput for Posted Writes 1.1.3. Throughput for Reads
1.3. Reference Design Functional Description x
1.3.1. File Naming Conventions 1.3.2. Project Hierarchy
1.7. Hardware Installation x
1.7.1. Programming using the .sof File
1. PCI Express High Performance Reference Design

1.12. Document Revision History

Table 14.  Document Revision History
Date Version Changes
December 2018 2.6 Updated Software Requirements links
April 2017 2.5 Made the following changes:
  • Clarified that the software installation is included in the design (.zip) file in the "Software Installation" section.
October 2015 2.4 Made the following changes:
  • Added Arria 10 devices globally.
  • Changed the example filename given in the "File Naming Conventions" section.
  • Changed the application given in the "Running the Software Application" section.
  • Changed abbreviation in the "Naming Conventions for Reference Design Variations" table.
  • Changed the directory name in the "Software Installation" section.
  • Changed the directory name in the "Running the Software Application" section.
December 2014 2.3 Changed the note in the "Performance Benchmarking Results" section.
December 2014 2.2 Made the following changes:
  • Added links to .zip files for supported devices.
  • Corrected file name abbreviations.
  • Updated steps for Software Installation.
  • Changed to use 64-bit software driver.
October 2014 2.1 Made the following changes:
  • This reference design uses the Cyclone IV GX FPGA Development Kit, not the Transceiver Starter Kit.
  • Listed Arria V GT, Cyclone V GT, and Stratix V GX development kits that run this reference design.
  • Simplied language to facilitate understanding by non-native English audience.
January 2014 2.0
  • Updated numbers for Stratix V Hard IP for PCI Express Performance
  • Added Cyclone V and Arria V GT Hard IP for PCI Express Performance numbers
February 2013 1.6
  • Clarified that the only Jungo driver that Altera delivers with this reference design is an executable file configured for the specific reference design. Altera does not provide you a Jungo driver for use in any other application.
  • Updated with current IP core names.

    This document update includes no technical changes in the reference design.

August 2012 1.5
  • Corrected bandwidths in Stratix V Hard IP for PCI Express Performance - Intel i7-3930K Processor.
July 2012 1.4
  • Updated to show the performance of the Stratix V GX (5SGXEA7K2F40C2NES) device running on the Stratix V GX FPGA Development Kit.
  • Removed performance tables for legacy devices.
August 2010 1.3
  • Updated to show the performance of the Cyclone IV GX (EP4CGX15) device running on the Cyclone IV GX Transceiver Starter Kit.
August 2009 1.2
  • Updated to show the performance of the Arria II GX (EP2AGX125) device running on the Arria II GX FPGA Development Kit.
May 2009 1.1
  • Updated to show the performance of the Stratix IV GX (EP4SGX230) device running on the Stratix IV GX FPGA Development Kit.
  • Added new commands to the PCI Express Performance Demo GUI.
May 2007 1.0 Initial release.
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