AN 456: PCI Express High Performance Reference Design

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ID 683541
Date 12/12/2018
Public
Document Table of Contents
Document Table of Contents x
1. PCI Express High Performance Reference Design
1. PCI Express High Performance Reference Design x
1.1. Understanding Throughput in PCI Express 1.2. Deliverables Included with the Reference Design 1.3. Reference Design Functional Description 1.4. Hardware Requirements 1.5. Software Requirements 1.6. Software Installation 1.7. Hardware Installation 1.8. Running the Software Application 1.9. Additional Chaining DMA Commands 1.10. Using SignalTap II 1.11. Performance Benchmarking Results 1.12. Document Revision History
1.1. Understanding Throughput in PCI Express x
1.1.1. Protocol Overhead 1.1.2. Throughput for Posted Writes 1.1.3. Throughput for Reads
1.3. Reference Design Functional Description x
1.3.1. File Naming Conventions 1.3.2. Project Hierarchy
1.7. Hardware Installation x
1.7.1. Programming using the .sof File
1. PCI Express High Performance Reference Design

1.3.1. File Naming Conventions

This reference design is available in many different configurations as shown in the following table. The file name for each configuration is created by concatenating the following variables:

<type>_<device_family>_<data_rate>_x<lanes>_<user_interface><datapath_width>

Table 1.  Naming Conventions for Reference Design Variations
Variable Abbreviation Value
Type hip Hard IP implementation
sip Soft IP implementation
Device_family civgx Cyclone IV GX
cvgt Cyclone V GT
cvgx Cyclone V GX
aiigx Arria II GX
avgt Arria V GT
a10gx Arria 10 GX
sivgx Stratix IV GX
svgx Stratix V GX
Data_rate g1 Gen1
g2 Gen2
g3 Gen3
Lanes N/A 1, 4, or 8
User_interface avst Avalon® Streaming (Avalon-ST)
Datapath_width 64 64 bit interface to the Application Layer
128 128 bit interface to the Application Layer

For example, the filename hip_sivgx_g2_x8_avst128 specifies a reference design for the following configuration:

  • Hard IP implementation
  • Stratix IV GX device
  • Gen2
  • Eight lanes
  • Avalon-ST interface with a 128 interface to the Application Layer.
Level Two Title