Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 1/07/2022
Public

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6.5.3.10.2. Insertion Delay

If the design requires a global signal, consider adding half a cycle to timing by using a negative-edge triggered register to generate the signal, and use a multicycle setup constraint.
Figure 44. Negative-Edge Triggered Register
Figure 45. Multicycle Setup Constraint
set_multicycle_path -from <generating_register> -setup -end 2