AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

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ID 683785
Date 5/13/2016
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Document Table of Contents
Document Table of Contents x
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices x
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench x
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals x
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers x
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1.3. Design Parameters

The reference designs allow you to set the total number of channels. The design with the IEEE 1588v2 allows you to also set the width of the timestamp fingerprint. You can specify these parameters by editing the altera_eth_top.sv file.

Table 2.  Parameters
Name Description Default Value
NUM_CHANNELS Use this parameter to specify the total number of Ethernet channels to be instantiated in the design. You can specify between 1 to 10 channels. 2
TSTAMP_FP_WIDTH

Use this parameter to set the width of the timestamp fingerprint width for the design. The value of this parameter must match the value of the Timestamp fingerprint width parameter of the Triple-Speed Ethernet MAC IP. Each time you change the value of this parameter, you must reconfigure and regenerate the MAC IP.

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