AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

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ID 683785
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices x
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench x
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals x
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers x
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1.8.1. Packet Classifier Interface Signals

Table 6.  Packet Classifier Interface SignalsThe packet classifier is one of the components in the design with the IEEE 1588v2 feature.
Signal Direction Width Description
tx_egress_timestamp_ request_in_valid[] In NUM_CHANNELS Assert this signal if a timestamp is required for the TX frame. Align this signal to the start of the packet.
tx_egress_timestamp_ request_in_fingerprint[][] In NUM_CHANNELS x TSTAMP_ FP_WIDTH Specifies the fingerprint of the TX frame for a given channel. You configure the width of the fingerprint using the TSTAMP_FP_WIDTH parameter.
clock_operation_mode[][] In NUM_CHANNELS x 2 Specifies the clock mode.
  • 00: Ordinary clock
  • 01: Boundary clock
  • 10: End to end transparent clock
  • 11: Peer to peer transparent clock
pkt_with_crc_mode[] In NUM_CHANNELS Assert the respective signal bit to indicate that the packet for the channel contains a CRC field. Otherwise, deassert the signal bit.
tx_ingress_timestamp_ valid[] In NUM_CHANNELS Assert the respective signal bit to allow the residence time of the channel to be updated based on the decoded results. Otherwise, deassert the signal bit.
tx_ingress_timestamp_96b_ data[][] In NUM_CHANNELS x 96 Specify the 96-bit ingress timestamp for the channel in the following format:
  • Bits 48 to 95: 48-bit seconds field.
  • Bits 16 to 47: 32-bit nanoseconds field.
  • Bits 0 to 15: 16-bit fractional nanoseconds field.
tx_ingress_timestamp_64b_ data[][] In NUM_CHANNELS x 64 Carries the 64-bit ingress timestamp for the channel in the following format:
  • Bits 16 to 63: 48-bit nanoseconds field.
  • Bits 0 to 15: 16-bit fractional nanoseconds field.
tx_ingress_timestamp_ format[] In NUM_CHANNELS Assert the respective signal bit to use the 64-bit timestamp format for the channel. When deasserted, the 96-bit timestamp format is used.

Align this signal to the start of the packet.

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