1.7.1. Testbench Files
The testbench files are located in the following folders:
- <project directory>/altera_eth_tse_wo_1588/testbench/Modelsim/testcase<n> for the reference design without the IEEE 1588v2 feature.
- <project directory>/altera_eth_tse_w_1588/testbench/Modelsim/testcase<n> for the reference design with the IEEE 1588v2 feature.
| Name | Description |
|---|---|
| avalon_bfm_wrapper.sv | A wrapper for the Avalon BFMs that the avalon_driver.sv file uses. |
| avalon_driver.sv | A SystemVerilog HDL driver that uses the BFMs to form the TX and RX datapaths, and access the Avalon-MM interface. |
| avalon_if_params_pkg.sv | A SystemVerilog HDL testbench that contains parameters to configure the BFMs. Because the configuration is specific to the DUT, you must not change the contents of this file. |
| avalon_st_eth_packet_monitor.sv | A SystemVerilog HDL testbench that monitors the Avalon-ST TX and RX interfaces. |
| default_test_params_pkg.sv | A SystemVerilog HDL package that contains the default parameter settings of the testbench. |
| eth_mac_frame.sv | A SystemVerilog HDL class that defines the Ethernet frames. The avalon_driver.sv file uses this class. |
| eth_register_map_params_pkg.sv | A SystemVerilog HDL package that maps addresses to the Avalon-MM control registers. |
| ptp_timestamp.sv | A SystemVerilog HDL class that defines the timestamp in the testbench. |
| tb_run.tcl | A Tcl script that starts a simulation session in the ModelSim simulation software. |
| tb_testcase.sv tb_testcase_1588.sv |
A SystemVerilog HDL testbench file that controls the flow of the testbench. |
| tb_top_n.sv tb_top_n_1588.sv |
The top-level testbench file consists of the device under test (DUT), a client packet generator, and a client packet monitor along with other logic blocks. |
| wave.do | A signal tracing macro script that the ModelSim simulation software uses to display testbench signals. |