AN 967: Multiple Device Synchronization in Digital Phased Array System

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ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

5. Conclusion

This application note describes the synchronization requirements in the DPA system.

It describes the use of the JESD204B/C Intel® FPGA IP core to implement the deterministic latency between data converters and FPGA devices. It also demonstrates the JESD204B/C protocol for data exchange between FPGA devices.

The SYSREF signal is the sideband signal for the JESD204B/C to implement the deterministic latency. It must be captured under stable conditions at the data converter and FPGA I/O. A clock or SYSREF scheme is proposed to meet the DPA system performance requirement and SYSREF sampling timing requirement. The appendix lists the details about the FPGA I/O timing constraints for SYSREF.

The guidelines of the FPGA logic design are introduced to show how to solve the misalignment issue caused by clock domain crossing. The SYSREF distribution logic is shown to highlight the method to duplicate the SYSREF signal to different event modules to implement the event trigger synchronization.

The on-board test results are provided which validates the architecture proposed by this application note.

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