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3.2.3. SYSREF Capture
SYSREF must be captured under stable conditions at the device's I/O boundary. Setup time and hold time must be satisfied, as shown in the following figure.
Figure 8. SYSREF I/O Timing
Typically, the same clock device known as the source-synchronous interface generates the clk_dev and SYSREF signals. The figure Clocks and JESD204B/C Interface in DPA System Synchronization in Clock/SYSREF Scheme illustrates the Clock and SYSREF Generator block. The phase skew between the clock and data can be controlled meticulously and have high tolerance for PVT variation as both the clock and data are generated by the same device.
The following figure shows the clk_dev and SYSREF phase relationship measured at the clock device output. Generally, each clk_dev or SYSREF pair must have the same delay on the PCB to guarantee the same phase relationship at the destination device input. To get the expected phase skew between clk_dev and SYSREF, you can set a proper delay for clk_dev or SYSREF, if the clock device supports adjusting the output delay.
Figure 9. clk_dev and SYSREF Phase Relationship at Clock Device Output
For FPGA devices, the setup time and hold time for SYSREF are design dependent. You must set I/O timing constraints for the SYSREF input pin. The compiler uses the timing constraint during compilation and generation of the timing report. Refer to FPGA I/O Timing Constraints for SYSREF for the details about the source-synchronous interface timing constraints in the TimeQuest Timing Analyzer and SYSREF I/O timing closure.
Generally, the clock device generates the SYSREF pulse with several clk_dev cycles. You can use a pulse recovery logic in the FPGA to get a single clock cycle sysref_rcvd signal and use it as the synchronization signal, as shown in the following figure.
Figure 10. Wide SYSREF Pulse Capture