External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Generating the EMIF Design Example with the Performance Monitor
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4
2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4 x
2.1.1.3.3.1. Guidelines for Selecting the LPDDR4 Component
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

2.3. Configuring DQ Pin Swizzling

It is important to strictly follow the pin placement for a given memory topology when assigning pin locations for your EMIF IP.

Do not change the location for the EMIF pin using a .qsf assignment or the pin planner if you need to swap the DQ pins within a DQS group or the DQS group to simplify board design. For example, if you implement a x32 DDR4 interface, the EMIF pin location must adhere to the x32 column in the DDR4 Pin Placement table in the Product Architecture chapter of the External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs . There is no flexibility to swap the address command pin location.

The following tables summarize the parameters for pin swizzling and byte swizzling, respectively.

Table 3.  User Extra Parameters for Swizzling the DQ Pin
Parameter Description
PIN_SWIZZLE_CH<m>_DQS<n>

Used for swizzling DQ pin within DQS group <n> for channel <m>.

m=0 only for DDR4.
PIN_SWIZZLE_CH<m>_ECC Used for swizzling DQ pin within the following lane:
  • ECC (When side-band ECC is enabled)
  • RUSER/WUSER lane (when Extra DQ Byte Lane is enabled)
m=0 only for DDR4
PIN_SWIZZLE_PRI_DQS<n> Used for swizzling DQ pin within DQS group <n> in the primary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.
PIN_SWIZZLE_SEC_DQS<n> Used for swizzling DQ pin within DQS group <n> in the secondary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.
PIN_SWIZZLE_PRI_ECC Used for swizzling DQ pin within the ECC lane or RUSER/WUSER lane (when the Extra DQ Byte Lane is enabled), if this lane is implemented in the primary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.
PIN_SWIZZLE_SEC_ECC Used for swizzling DQ pin within the ECC lane or RUSER/WUSER lane (when the Extra DQ Byte Lane is enabled), if this lane is implemented in the secondary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.

For device widths of x4 and x8, you can swizzle each DQ pin within its DQS group. For device widths of x16, you can swizzle each DQ pin within the lower byte and upper byte respectively. You cannot swizzle DQ pin for the lower byte to upper byte and vice versa.

Table 4.  User Extra Parameters for Byte Swizzling
Parameter Description
BYTE_SWIZZLE_CH<m>

Used for swizzling DQS group for CH<m> of the interface.

m=0 for DDR4.
BYTE_SWIZZLE_PRI Used for swizzling DQS group in the primary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.
BYTE_SWIZZLE_SEC Used for swizzling DQS group in the secondary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.

Example: DQ Pin Swizzling Within DQS group for x32+ECC DDR4 interface

This example uses the lane placement of the following table, with a x8 DQ width.

Table 5.  Lane Placement for a x32+ECC DDR4 Interface
Lane Number BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
Default placement DQ[0] AC0 AC1 AC2 DQ[1] DQ[2] DQ[3] GPIO
Table 6.  Example of Swizzling DQ pin in BL0 ( DQS group 0)
Lane Pin Index DDR4 x32 (Default Placement) After Swizzling / Swapping
BL0 11 MEM_DQ[7] MEM_DQ[6]
10 MEM_DQ[6] MEM_DQ[5]
9 MEM_DQ[5] MEM_DQ[7]
8 MEM_DQ[4] MEM_DQ[4]
7    
6 MEM_DM_N[0] MEM_DM_N[0]
5 MEM_DQS_C[0] MEM_DQS_C[0]
4 MEM_DQS_T[0] MEM_DQS_T[0]
3 MEM_DQ[3] MEM_DQ[0]
2 MEM_DQ[2] MEM_DQ[2]
1 MEM_DQ[1] MEM_DQ[1]
0 MEM_DQ[0] MEM_DQ[3]

To achieve this swizzling in DQS group 0, you must enter PIN_SWIZZLE_CH0_DQS0=3,1,2,0,4,7,5,6; in the User Extra Parameters field of the Additional Parameters tab in the Advanced Parameters section of the General IP Parameters tab in the External Memory Interfaces IP parameter editor.

Figure 21. Entering a PIN_SWIZZLE Specification
Table 7.  Example of Swizzling DQ pin in BL5 ( DQS group 2)
Lane Pin Index DDR4 x32 (from table) After Swizzling / Swapping
BL5 71 MEM_DQ[23] MEM_DQ[17]
70 MEM_DQ[22] MEM_DQ[22]
69 MEM_DQ[21] MEM_DQ[21]
68 MEM_DQ[20] MEM_DQ[20]
67    
66 MEM_DM_N[2] MEM_DM_N[2]
65 MEM_DQS_C[2] MEM_DQS_C[2]
64 MEM_DQS_T[2] MEM_DQS_T[2]
63 MEM_DQ[19] MEM_DQ[19]
62 MEM_DQ[18] MEM_DQ[18]
61 MEM_DQ[17] MEM_DQ[23]
60 MEM_DQ[16] MEM_DQ[16]

To achieve this swizzling in DQS Group 2, you must enter PIN_SWIZZLE_CH0_DQS2=16,23,18,19,20,21,22,17; in the User Extra Parameters field of the Additional Parameters tab in the Advanced Parameters section of the General IP Parameters tab in the External Memory Interfaces IP parameter editor.

Figure 22. Entering a PIN_SWIZZLE Specification

You can enter multiple specifications in the User Extra Parameters field, each separated by a semicolon.

Figure 23. Entering Multiple PIN_SWIZZLE Specifications

Example: Byte Swizzling for a x32 DDR4 interface, implemented with a Memory Device of x8 Width

Table 8.  Lane Placement for x32 DDR4 Interface
Lane Number BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
Default Placement DQ[0] AC[0] AC[1] AC[2] DQ[1] DQ[2] DQ[3] GPIO
After Byte Swizzling DQ[2] AC[0] AC[1] AC[2] DQ[1] DQ[0] DQ[3] GPIO
BYTE SWIZZLE 2 X X X 1 0 3 X

This example illustrates swizzling DQS group 0 with DQS group 2. The BYTE_SWIZZLE_CH0 denotes the DQS group implemented in the lane after the swizzling. X indicates that the lane is not used as a data lane (meaning that it serves as an address/command lane or is not used by the EMIF interface).

To achieve this swizzling, you must enter BYTE_SWIZZLE_CH0=2,X,X,X,1,0,3,X; in the User Extra Parameters field of the Additional Parameters tab in the Advanced Parameters section of the General IP Parameters tab in the External Memory Interfaces IP parameter editor.

Figure 24. Swizzling DQS group 0 with DQS group 2

Example : Combining Pin and Byte Swizzling

This example combines the two previous examples, entering the following swizzle parameters:

  • PIN_SWIZZLE_CH0_DQS0=3,1,2,0,4,7,5,6;
  • PIN_SWIZZLE_CH0_DQS2=16,23,18,19,20,21,22,17;
  • BYTE_SWIZZLE_CH0=2,X,X,X,1,0,3,X;

The following table shows the resulting pin placement after DQ pin and byte swizzling.

Table 9.  Lane Placement for Combining Pin and Byte Swizzling Placement
Lane Pin Index Default Effective Pinout
BL5 71 MEM_DQ[23] MEM_DQ[6]
70 MEM_DQ[22] MEM_DQ[5]
69 MEM_DQ[21] MEM_DQ[7]
68 MEM_DQ[20] MEM_DQ[4]
67    
66 MEM_DM_N[2] MEM_DM_N[0]
65 MEM_DQS_C[2] MEM_DQS_C[0]
64 MEM_DQS_T[2] MEM_DQS_T[0]
63 MEM_DQ[19] MEM_DQ[0]
62 MEM_DQ[18] MEM_DQ[2]
61 MEM_DQ[17] MEM_DQ[1]
60 MEM_DQ[16] MEM_DQ[3]
BL0 11 MEM_DQ[7] MEM_DQ[17]
10 MEM_DQ[6] MEM_DQ[22]
9 MEM_DQ[5] MEM_DQ[21]
8 MEM_DQ[4] MEM_DQ[20]
7    
6 MEM_DM_N[0] MEM_DM_N[2]
5 MEM_DQS_C[0] MEM_DQS_C[2]
4 MEM_DQS_T[0] MEM_DQS_T[2]
3 MEM_DQ[3] MEM_DQ[19]
2 MEM_DQ[2] MEM_DQ[18]
1 MEM_DQ[1] MEM_DQ[23]
0 MEM_DQ[0] MEM_DQ[16]
Example: Swizzling for a x32 + ECC DDR4 interface
Table 10.  Lane Placement for x32 + ECC DDR4 Interface
Lane Number BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
DDR4_AC_TOP DQ[4] DQ[3] DQ[2] DQ[1] AC1 AC2 AC3 sDO[0]
DQS Group Number in Byte Swizzling Notation 3 2 1 0 AC1 AC2 AC0 ECC
BYTE SWIZZLE 3 2 0 1 X X X ECC

In this example, BL7 cannot be swapped with other used DQS group. It is used as follows:

  • RUSER/WUSER Lane in x40 configuration
  • ECC Lane in x32 + ECC configuration

This example illustrates swizzling DQS group 1 (BL3) with DQS group 0 (BL2).

To achieve this swizzling, enter the following BYTE_SWIZZLE_CH0 specifications in the USER Extra Parameters filed:

BYTE_SWIZZLE_CH0=2,X,X,X,1,0,3,ECC;

In a DDR4 x32 + ECC configuration, the highest index DQS group is used as the ECC lane. We use PIN_SWIZZLE_CH0_ECC for swizzling the DQ pins within the ECC lane in this case. Note that the valid value for pin swizzling specification in the ECC lane is always 0-7 only.

Table 11.  Example of DQ Pin Swizzling in ECC Lane
Lane Pin Index Default Effective Pinout
BL7 95 MEM_DQ{39] MEM_DQ{36]
94 MEM_DQ{38] MEM_DQ{37]
93 MEM_DQ{37] MEM_DQ{38]
92 MEM_DQ{36] MEM_DQ{39]
91    
90 MEM_DM_N[4] MEM_DM_N[4]
89 MEM_DQS_C[4] MEM_DQS_C[4]
88 MEM_DQS_T[4] MEM_DQS_T[4]
87 MEM_DQ{35] MEM_DQ{34]
86 MEM_DQ{34] MEM_DQ{35]
85 MEM_DQ{33] MEM_DQ{32]
84 MEM_DQ{32] MEM_DQ{33]

To achieve the pin swizzling shown in the above table, enter the following BYTE_SWIZZLE_CH0 specifications in the USER Extra Parameters: 

PIN_SWIZZLE_CH0_ECC=1,0,3,2,7,6,5,4;
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