4. Document Revision History for External Memory Interfaces (EMIF) IP...

External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394

Date 4/01/2024

Version 24.1-6.1.0

Public

Visible to Intel only — GUID: cvl1682533601448

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Document Table of Contents

Document Table of Contents x

1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

1. About the External Memory Interfaces Agilex™ 5 FPGA IP x

1.1. Release Information

2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x

2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Generating the EMIF Design Example with the Performance Monitor

2.1. Creating an EMIF Project x

2.1.1. Generating a Custom Memory Presets File

2.1.1. Generating a Custom Memory Presets File x

2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File

2.1.1.3. Examples for Generating a Custom Memory Presets File x

2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4

2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4 x

2.1.1.3.3.1. Guidelines for Selecting the LPDDR4 Component

2.2. Generating and Configuring the EMIF IP x

2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File

3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x

3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab

3.2. Simulation Design Example x

3.2.1. Running Simulation

1. About the External Memory Interfaces Agilex™ 5 FPGA IP

1.1. Release Information

2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP

2.1. Creating an EMIF Project

2.1.1. Generating a Custom Memory Presets File

2.1.1.1. Memory Device Description IP Parameter Editor Guidelines

2.1.1.2. Saving a Memory Device Presets File

2.1.1.3. Examples for Generating a Custom Memory Presets File

2.1.1.3.1. Generating a Custom Memory Preset File for DDR4

2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type

2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4

2.1.1.3.3.1. Guidelines for Selecting the LPDDR4 Component

2.2. Generating and Configuring the EMIF IP

2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines

2.2.2. Using Custom Memory Device Presets from a File

2.3. Configuring DQ Pin Swizzling

2.4. Generating the Synthesizable EMIF Design Example

2.5. Generating the EMIF Design Example for Simulation

2.6. Pin Placement for Agilex™ 5 EMIF IP

2.7. Compiling the Agilex™ 5 EMIF Design Example

2.8. Generating the EMIF Design Example with the Performance Monitor

3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP

3.1. Synthesis Design Example

3.2. Simulation Design Example

3.2.1. Running Simulation

3.3. Example Design Tab

4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

Visible to Intel only — GUID: cvl1682533601448

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