Intel® Arria® 10 SoC Development Kit User Guide

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ID 683227
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Components 6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide A. Additional Information
1. Intel® Arria® 10 SoC Development Kit Overview x
1.1. General Description 1.2. Board Component Blocks 1.3. Recommended Operating Conditions 1.4. Handling the Board
2. Getting Started x
2.1. Board Inspection 2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software 2.3. Installing the Intel® SoC Embedded Development Suite (EDS) 2.4. Development Kit Installer 2.5. Installing the Intel® FPGA Download Cable Driver 2.6. SD Card Image with Example Software
2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software x
2.2.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe* Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Components x
5.1. Board Overview 5.2. Featured Device: Intel® Arria® 10 SoC 5.3. MAX V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over On-Board Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. On-Board Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughtercards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Additional Information x
A.1. Compliance and Conformity Statements
A.1. Compliance and Conformity Statements x
A.1.1. CE EMI Conformity Caution
1. Intel® Arria® 10 SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Components
6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide
A. Additional Information

5.1. Board Overview

This section provides an overview of the Intel® Arria® 10 SoC development board, including an annotated board image and component descriptions. The figure below shows an overview of the board features.

Figure 30. Overview of the Intel® Arria® 10 SoC Development Board
Table 13.  Board Components
Board Reference Type Description
Featured Devices
U23 FPGA Intel® Arria® 10 SoC, 10AS066N3F40E2SG, 1517-pin FBGA
U16 CPLD MAX V CPLD System Controller, 5M2210ZF256, 256-pin FBGA
U21 CPLD IO_MUX_CPLD, 5M2210F256, 256-pin FBGA
Configuration, Status, and Setup Elements
J24

(JTAG)

 JTAG chain header Provides access to the JTAG scan chain and disables the on-board Intel® FPGA Download Cable II when using an external JTAG debugger such as a Intel® FPGA Download Cable cable.
SW3 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.
SW4 MSEL DIP Switch Controls the configuration scheme on the board. MSEL pin 0, 1 and 2 connect to the DIP switch.
J22

(MICRO_USB_CONN)

 Micro-USB header USB interface to on-board Intel® FPGA Download Cable II JTAG for programming and debugging HPS, FPGA, or MAX V CPLD via a type-B Micro-USB cable.
SW1 Function Dip switch Selects I2C Master, Controls PCIe* slot power, and selects FPGA image source.
S8 Program select push button Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.
S7 Configure push button Load image from flash memory to the FPGA based on the settings of the program select LEDs.
D18 Configuration done LED Illuminates when the FPGA is configured.
D19 Load LED Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.
D17 Error LED Illuminates when the FPGA configuration from flash memory fails.
D42 Power LED Illuminates when 3.3-V power is present.
D13, D14 JTAG TX/RX LEDs Indicates the transmit or receive activity of the JTAG chain. The TX and RX LEDs flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle.
D20-D22 Program select LEDs Illuminates to show which flash memory image loads to the FPGA when you press the program select push button.
D23, D24 FMC port present LEDs Illuminates when a daughtercard is plugged into the FMC port.
D11, D12 UART LEDs Illuminates when UART transmitter and receiver are in use.
Clock Circuitry
U42 Multi-output oscillator Si5338A quad-output fixed oscillator with 156.25 MHz, 100 MHz, 25 MHz, and 100 MHz outputs.
U54 148.5-MHz Oscillator Programmable oscillator with a default frequency of 148.5 MHz. The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.
U51 50-MHz oscillator 50.000 MHz crystal oscillator for general purpose logic
U11 Multi-output oscillator Two 100 MHz outputs for PCIe* application
J13, J14 Clock input SMA connector External clock inputs for the transceiver test port
J15 HPS SMA clock Drives LVCMOS to HPS clock multiplexer.
U50 Multi-output oscillator Si5338A quad-output fixed oscillator with 125 MHz, 270MHz, 100 MHz, and 100 MHz outputs.
U49 Multi-output oscillator Si5338A quad-output fixed oscillator with four 133.33 MHz outputs.
U26 Multi-output clock cleaner LMK04828 Clock cleaner
General User Input/Output
D25-D32 User LEDs Four user LEDs and four HPS LEDs. Illuminate when driven low.
SW2 User DIP switch User DIP switch. When the switch is ON, a logic 0 is selected.
S10 FPGA reset push button Reset the FPGA logic
S9 HPS External Interrupt Push button HPS external interrupt
S3-S6

S11-S14

 General user push buttons Four user push buttons and four HPS push buttons. Driven low when pressed.
S1, S2 HPS reset push buttons HPS cold/warm reset push buttons
Memory Connectors
J26 HPS HILO Memory connector HPS memory card include DDR3 HILO memory card and DDR4 HILO memory card
J23 Boot Flash Connector Boot flash card options include QSPI flash card, SD micro flash card and NAND flash card
J27 FPGA HILO Connector FPGA memory card options include DDR3 HILO memory card , and DDR4 HILO memory card
U19 EPCQ Flash EPCQ flash for FPGA AS configuration
U45 I2C EEPROM 32-Kb I2C serial EEPROM
Communication Ports
J57 PCIe* socket GEN3 x8 Socket
J29, J19 FMC port J29 is a V57.1 compatible FMC connector. J19 is a FMC connector defined by Intel 16 transceivers specification
J7, J8 SFP+ port Two SFP+ ports
U12, J5 Gigabit Ethernet port RJ-45 connectors that provide HPS 10/100/1000 Ethernet connections via a Micrel KSZ9031RN PHY.
U8, J2

(Port 1)

 Gigabit Ethernet port SGMII Gigabit Ethernet port through FPGA transceiver
U9, J3

(Port 2)

 Gigabit Ethernet port SGMII Gigabit Ethernet port through FPGA transceiver
J10, U13

(UART 1)

 USB-UART Port Mini-B USB interface to USB-to-UART bridge for serial UART interface.
J25 DB9 UART port DB9 RS-232 UART Port
U22, J4

(USB 2.0)

 USB OTG port USB 2.0 On-The-Go (OTG) interface.
U5 Real-time clock DS1339 device with built-in power sense circuit that detects power failures and automatically switches to backup battery supply, maintaining time keeping even when the board is not powered.
J43

(HPS TRACE)

 Mictor-38 4-bit Trace for HPS debug
J20

(FPGA TRACE)

 Mictor-38 FPGA 16-bit Trace
Video and Display Ports
J35 Character LCD Connector that interfaces to the included 16 character × 2 line LCD module along with two standoffs.
J36 Display port connector Display port interface
U29, J48

(SDI_TXBNC_P)

 SDI Video output port HDBNC 75-Ohm SDI video TX interface
U30, J49

(SDI_IN_P1)

 SDI Video input port HDBNC 75-Ohm SDI video RX interface
Power Supply
J36 DC input jack Accepts 12-V DC power supply
SW5 Power switch Switch to power on or off the board when power is supplied from the DC input jack.
Level Two Title