Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

29.1. About the Scaler

The Scaler Intel FPGA IP resizes the fields in an Intel FPGA streaming video compliant input to produce output fields of a different height and or width. The IP supports both full and lite variants of interface protocol. The scaler offers three algorithms for resizing images: nearest neighbor, bilinear and polyphase. The three algorithms offer three cost vs quality options. Nearest neighbor offers the lowest FPGA resource cost and the lowest output image quality and polyphase offers the highest quality at the highest cost.

The scaler can resize an incoming video field to produce an output field of any size, restricted only by defined minimum and maximum widths and heights. You set the desired output field width and height at runtime via the register map (if the Avalon memory-mapped control agent interface is enabled), or via fixed parameters (if the Avalon memory-mapped control agent interface is not enabled). Full variants define the input field width and height by the image info packets received at the input interface. Lite variants define the input field width and height via the register map. With defined input and output widths and heights, the scaler applies the correct horizontal and vertical scaling ratios (which may be different).

The following bounds apply to the input and output field widths.

  • Input field width must be less than or equal to the value set in the maximum input field width parameter.
  • Output field width must be less than or equal to the value set in the maximum output field width parameter
  • Output field width must be greater than or equal to the value set in the number of pixels in parallel parameter

You may also choose to turn off scaling in the horizontal or vertical directions if either is not required. In this case, the output width or height is unaltered, regardless of the settings in the register map. Also, the scaler only supports scaling for video with 4:4:4 chroma siting. Full variants assert the error flag for any of these restrictions.