Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

24.3. Genlock Signal Router IP Interfaces

Table 352.  Genlock Signal Router IP Interfaces
Name Direction Width Description
Clocks and Resets
vid_clk In 1 Reserved
vid_reset In 1 Reserved
axi4s_fr_vid_in_clk In 1 Optional Input clock associated with each of the full-raster interfaces
axi4s_fr_vid_in_reset In 1 Optional Input reset associated with each of the full-raster interfaces
async_clk In 1 Optional Input clock associated with each of the discrete and clocks only interfaces
cpu_clock In 1 Control interface clock
cpu_reset In 1 Control interface reset
Control Interfaces
av_mm_control_agent_address In 7 Avalon memory-mapped agent address
av_mm_control_agent_write In 1 Avalon memory-mapped agent write
av_mm_control_agent_writedata In 32 Avalon memory-mapped agent write data
av_mm_control_agent_byteenable In 4 Avalon memory-mapped agent byte enable
av_mm_control_agent_read In 1 Avalon memory-mapped agent read
av_mm_control_agent_readdata Out 32 Avalon memory-mapped agent read data
av_mm_control_agent_readdatavalid Out 1 Avalon memory-mapped agent read
av_mm_control_agent_waitrequest Out 1 Avalon memory-mapped agent wait request
Intel FPGA streaming video interfaces (Optional per input interface)
axi4s_fr_vid_in_tdata In 61 AXI4-S data in
axi4s_fr_vid_in_tvalid In 1 AXI4-S data valid
axi4s_fr_vid_in_tuser[0] In 1 AXI4-S start of video frame
axi4s_fr_vid_in_tuser[N-1:1] In 62 Unused
axi4s_fr_vid_in_tlast In 1 AXI4-S end of packet
axi4s_fr_vid_in_tready Out 1 AXI4-S data ready
Intel FPGA Discrete Timing Signals (Optional per input interface)
async_clock In 1 Input clock
async_f In 1 Field
async_v In 1 Vertical blanking
async_h In 1 Horizontal blanking
async_v_sync In 1 Vertical sync
async_h_sync In 1 Horizontal sync
async_toggle In 1 Start of frame toggle
axi4s_pulse In 1 Start of frame pulse
Intel FPGA Clocks only signal (Optional per output interface)
genlock_clock In 1 Output Clock
Intel FPGA Discrete Timing Signals (Optional per input interface)
genlock_clock In 1 Input Clock
genlock_f In 1 Field
genlock_v In 1 Vertical blanking
genlock_h In 1 Horizontal blanking
genlock_sof_toggle In 1 Start of frame toggle
genlock_sof_pulse In 1 Start of frame pulse
61

The equation gives the TDATA width for interfaces for full-raster variants:

max (floor(((bits per color sample x (number of color planes + 1) x pixels in parallel) + 7) / 8) x 8, 16)

62

This equation gives the TUSER width N for these interfaces: ceil (tdata width / 8)