AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

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ID 683183
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report x
Hardware Requirements Hardware Setup AD9371 EVM Software Setup Hardware Checkout Methodology for JESD204B Transmitter JESD204B IP Core and DAC Configurations Hardware Checkout Methodology for JESD204B Receiver JESD204B IP Core and Main ADC Configurations Deterministic Latency (Subclass 1) Test Results Test Result Comments Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Hardware Checkout Methodology for JESD204B Transmitter x
Transmitter Data Link Layer Transmitter Transport Layer Scrambling
Transmitter Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Hardware Checkout Methodology for JESD204B Receiver x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

Code Group Synchronization (CGS)

Table 1.  CGS Test Cases

Test Case

Objective

Description

Passing Criteria

TX_CGS.1

Check that /K/ characters are transmitted when sync_n is asserted.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1:0] 1

The following signals in <ip_variant_name>.v are tapped:

  • sync_n
  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the Signal Tap.

Each lane is represented by 32-bit data bus in jesd204_tx_pcs_data. The 32-bit data bus for is divided into 4 octets.

  • /K/ character or K28.5 (0xBC) is transmitted at each octet of the jesd204_tx_pcs_data bus when the receiver asserts the sync_n signal.
  • The jesd204_tx_pcs_kchar_data signal is asserted whenever control characters like /K/ characters are transmitted.
  • The jesd204_tx_int is deasserted if there is no error.

TX_CGS.2

Check that /K/ characters are transmitted after sync_n is deasserted but before the start of multiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1:0] 1

The following signals in <ip_variant_name>.v are tapped:

  • sync_n
  • tx_sysref
  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the Signal Tap.

Each lane is represented by 32-bit data bus in the jesd204_tx_pcs_data signal. The 32-bit data bus is divided into 4 octets.

Check the following status and error in the AD9371 register:

  • 8b/10b Not-in-Table Error
  • 8b/10b Disparity Error
  • Unknown K character Error
  • The /K/ character transmission continues for at least 1 frame plus 9 octets.
  • The sync_n and jesd204_tx_int signals are deasserted.
  • On reading status using ‘MYKO-NOS_deframerGetIrq’ API, “Not-in-table error”, “Bad Disparity error”, and “Unknown K character error” registers should not be set.
1 L is the number of lanes.
Level Two Title