AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

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ID 683183
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report x
Hardware Requirements Hardware Setup AD9371 EVM Software Setup Hardware Checkout Methodology for JESD204B Transmitter JESD204B IP Core and DAC Configurations Hardware Checkout Methodology for JESD204B Receiver JESD204B IP Core and Main ADC Configurations Deterministic Latency (Subclass 1) Test Results Test Result Comments Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Hardware Checkout Methodology for JESD204B Transmitter x
Transmitter Data Link Layer Transmitter Transport Layer Scrambling
Transmitter Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Hardware Checkout Methodology for JESD204B Receiver x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

Transmitter Transport Layer

To verify the data integrity of the payload data stream through the JESD204B transmitter IP core and transport layer and to verify that data from the FPGA digital domain is successfully sent to the DAC analog domain, the FPGA is configured to generate a monotone sine wave. Connect an oscilloscope/spectrum analyzer to observe the waveform/spectrum of a singletone at the DAC analog channels.

The AD9371 upconverts signal to RF frequency. This RF frequency is tunable by the user and specified to AD9371 as LO frequency. Depending on the phase of I and Q streams, the output frequency at DAC analog channels will be LO frequency ± monotone frequency. In our configuration the output frequency will be observed to be LO frequency – monotone frequency.

Figure 7. Data Integrity Check Using Sine WaveThe following figure shows the conceptual test setup for data integrity checking.

The Signal Tap II Logic Analyzer tool monitors the operation of the transmitter transport layer.

Table 3.  Transport Layer Test Cases

Test Case

Objective

Description

Passing Criteria

TX_TL.1

Verify the data transfer from digital to analog domain.

Enable sine wave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.

A monotone sine wave is observed on the oscilloscope.
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