Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.2. Clipper II Control Registers

Table 36.  Clipper II Control Register MapThe control data is read once at the start of each frame and is buffered inside the Clipper II IP core, so the registers can be safely updated during the processing of a frame.
Address Register Description
0 Control Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the IP core to stop the next time control information is read.

When you enable run-time control, the Go bit gets deasserted by default. If you do not enable run-time control, the Go is asserted by default.

1 Status Bit 0 of this register is the Status bit, all other bits are unused. The Clipper IP core sets this address to 0 between frames. It is set to 1 while the IP core is processing data and cannot be stopped.
2 Interrupt This bit is not used because the IP core does not generate any interrupts.
3 Left Offset The left offset, in pixels, of the clipping window/rectangle.
Note: The left and right offset values must be less than or equal to the input image width.
4 Right Offset or Width In clipping window mode, the right offset of the window. In clipping rectangle mode, the width of the rectangle.
Note: The left and right offset values must be less than or equal to the input image width.
5 Top Offset The top offset, in pixels, of the clipping window/rectangle.
Note: The top and bottom offset values must be less than or equal to the input image height.
6 Bottom Offset or Height In clipping window mode, the bottom offset of the window. In clipping rectangle mode, the height of the rectangle.
Note: The top and bottom offset values must be less than or equal to the input image height.