Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021
Public

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16.7.3. Memory Map for Frame Reader or Writer Configurations

When creating content for on-screen display using a frame reader, or when processing frame data written to DDR through a frame writer, it is necessary to understand the memory mapping used by the Frame Buffer II IP core.

The frame data is tightly packed into memory and aligned on frame (or field) boundaries to minimize storage usage and maximize memory bandwidth usage.

The figure below shows an example of memory map for a frame buffer with the configuration settings below:

  • Bits per pixel per color sample = 8 bits
  • Number of color planes = 2
  • Pixels in parallel = 1
  • Avalon-MM master(s) local ports width = 25
  • Av-MM burst target Write = 32
  • Av-MM burst target Read = 32
  • Align read/write bursts on read boundaries = On
  • Maximum ancillary packets per frame = 10
  • Frame buffer memory base address = 0x6800 0000
  • Enable use of inter-buffer offset = On
  • Inter-buffer offset = 0x0100 0000
  • Delay length (frames) = 1

The maximum length of ancillary packets is ignored if you turn on Align read/write bursts on read boundaries.

Figure 68. Example of Memory Map for Base Address 0x6800_0000

The ancillary (user) packets are located in memory after the frame storage when you enable Align read/write bursts on read boundaries. Each packet will be offset in memory by (Avalon-MM local ports width * burst target )/8. In this example configuration, the offset is 256*32 / 8 = 1024 (0x400)

Therefore, for the 3 buffers configured, any ancillary packets are written to memory at the following addresses:

Anc buffer 0, anc packet 0 = 0X6B00_0000

Anc buffer 0, anc packet 1 = 0X6B00_0000 + 1*0x400 = 0X6B00_0400

Anc buffer 0, anc packet 2 = 0X6B00_0000 + 2*0x400 = 0X6B00_0800

... Anc buffer 0, anc packet 9 = 0X6B00_0000 + 9*0x400 = 0X6B00_2400

Anc buffer 1, anc packet 0 = 0X6B00_2800

Anc buffer 1, anc packet 1 = 0X6B00_2800 + 1*0x400 = 0X6B00_2800

Anc buffer 1, anc packet 2 = 0X6B00_2800 + 2*0x400 = 0X6B00_2B00...

... Anc buffer 1, anc packet 9 = 0X6B00_2800 + 9*0x400 = 0X6B00_4C00

Anc buffer 2, anc packet 0 = 0X6B00_5000

Anc buffer 2, anc packet 1 = 0X6B00_5000 + 1*0x0400 = 0X6B00_5400

Anc buffer 2, anc packet 2 = 0X6B00_5000 + 2*0x0400 = 0X6B00_5800...

... Anc buffer 2, anc packet 9 = 0X6B00_5000 + 9*0x0400 = 0X6B00_7400

Figure 69. Memory Map for Base Address 0x1000_0000 for Non 8-Bit Pixel ValuesThe figure below illustrates the aliasing that occurs in memory for non 8-bit pixel values that you need to take into account when generating or using pixel addresses in DDR.

The least significant bit (LSB) of the lead pixel is held in the LSB of the first memory word.