Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021
Public

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16.7. Frame Buffer Control Registers

A run-time control can be attached to either the writer component or the reader component of the Frame Buffer II IP core but not to both. The width of each register is 32 bits.

Table 55.  Frame Buffer II Control Register MapThe table below describes the register map for the Frame Buffer II IP core when configured as a Frame reader only (Reader column), Frame writer only (Writer column) or as a frame buffer (Buffer column). Y indicates the register is applicable for the feature and N/A means not applicable.
Note: Registers 3 and 4 return differently, depending on whether the register interface is a reader or writer control.
Address Register Reader Writer Buffer Type Description
0 Control Y Y Y RW Bit 0 of this register is the Go bit, Setting this bit to 0 causes the IP core to stop the next time control information is read.

When you enable run-time control, the Go bit gets deasserted by default. If you do not enable run-time control, the Go is asserted by default.

1 Status Y Y Y RO Bit 0 of this register is the Status bit, all other bits are unused.
2 Interrupt Y Y Y RW The frame writer raises its interrupt line and sets bit 0 of this register when the IP core writes a frame to DDR and the frame is ready to be read. You can clear the interrupt by writing a 1 to this bit.

The frame reader raises its interrupt line and sets bit 0 of this register when a complete frame is read from DDR. You can clear the interrupt by writing a 1 to this bit.

3 Frame Counter Y Y Y RO For a writer control interface, the counter is incremented if the frame is not dropped.

For a reader control interface, this counter is incremented if the frame is not repeated.

4 Drop/Repeat Counter Y Y Y RO For a writer control interface, the counter is incremented if the frame is dropped.

For a reader control interface, this counter is incremented if the frame is repeated.

5 Frame Information Y Y N/A RW
  • Bit 31 of this register is the Available bit used only in the frame writer mode. A 0 indicates no frame is available and a 1 indicates the frame has been written and available to read.
    Note: In Frame Writer only mode, you must acknowledge each available frame before the next frame is available. Refer to the acknowledge bit in the Misc register.
  • Bit 30 of this register is unused.
  • Bits 29 to 26 contain the interlaced bits of the frame last written by the buffer.
  • Bits 25 to 13 of this register contain the width of the frame last written by the buffer.
  • Bits 12 to 0 of this register contain the height of the frame last written by the buffer.
6 Frame Start Address Y Y N/A RW This register holds the frame start address for the frame last written to DDR by the writer.

If configured as a Reader only, you must write the frame start address to this register.

For the frame writer configuration, the frame start address is valid only when the Available bit in the Frame Information register is set.

7 Frame Reader Y N/A N/A RO
  • Bit 26 of this register is the Ready bit. This bit is set when the reader is ready to accept the details of the next frame to be read.
  • Bits 25 to 13 of this register indicate the maximum width of frames that may be read, as configured in the parameter editor.
  • Bits 12 to 0 of this register indicate the maximum height of frames that may be read, as configured in the parameter editor.
8 Misc Y Y Y RW
  • Bit 0 of this register is the acknowledge bit.
    • Applies only to Frame Writer only mode.
    • Set this bit to 1 to indicate that the available frame has been completely handled (refer to Available bit in the Frame Information register).
    • Writing a 1 triggers the buffer to be reset and the Frame Writer reuses the buffer.
  • Bit 1 of this register is the user packet affinity bit.
    • Set this bit to 1 you want to drop and repeat user packets together with their associated video packet (this is the next video packet received). This mode allows for specific frame information that must be retained with each frame.
    • Set this bit to 0 if all user packets are to be produced as outputs in order, regardless of any dropping or repeating of associated video packets. This mode allows for audio or closed caption information.
  • Bits 15 to 2 of this register are unused.
  • Bits 27 to 16 of this register contain the frame delay. The default delay value is 1, but you may introduce additional delay to the buffer by writing a value from 2 to 4095 to this register.
9 Locked Mode Enable N/A N/A Y RW Bit 0 of this register is enables locked mode. When you set the locked mode bit, the specified Input Frame Rate and Output Frame Rate registers tightly control the dropping and repeating of frames.

Setting this bit to 0 switches off the controlled rate conversion and returns the triple-buffering algorithm to a free regime where dropping and repeating is only determined by the status of the spare buffer. Other bits are unused.

10 Input Frame Rate N/A N/A Y RW Bits 15:0 contains a short integer value that corresponds to the input frame rate. Other bits are unused.
11 Output Frame Rate N/A N/A Y RW Bits 15:0 contains a short integer value that corresponds to the output frame rate. Other bits are unused.