Virtual JTAG Intel® FPGA IP Core User Guide

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ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

Applications of the Virtual JTAG Intel® FPGA IP Core

You can instantiate single or multiple instances of the Virtual JTAG Intel® FPGA IP core in your HDL code. During synthesis, the Intel® Quartus® Prime software assigns unique IDs to each instance, so that each instance is accessed individually. You can instantiate up to 128 instances of the Virtual JTAG Intel® FPGA IP core. The figure below shows a typical application in a design with multiple instances of the IP core.
Figure 2. Application Example

The hub automatically arbitrates between multiple applications that share a single JTAG resource. Therefore, you can use the IP core in tandem with other on‑chip debugging applications, such as the Signal Tap logic analyzer, to increase debugging visibility. You can also use the IP core to provide simple stimulus patterns to solicit a response from the design under test during run‑time, including the following applications:

  • To diagnose, sample, and update the values of internal parts of your logic. With this IP core, you can easily sample and update the values of the internal counters and state machines in your hardware device.
  • To build your own custom software debugging IP using the Tcl commands to debug your hardware. This IP communicates with the instances of the Virtual JTAG Intel® FPGA IP core inside your design.
  • To construct your design to achieve virtual inputs and outputs.
  • If you are building a debugging solution for a system in which a microprocessor controls the JTAG chain, you cannot use the Signal Tap logic analyzer because the JTAG control must be with the microprocessor. You can use low‑level controls for the JTAG port from the Tcl commands to direct microprocessors to communicate with the Virtual JTAG Intel® FPGA IP core inside the device core.
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