Virtual JTAG Intel® FPGA IP Core User Guide

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ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.08.12 20.3 Corrected the table title to: USER0 and USER1 Instruction Values in the SLD_NODE Discovery and Enumeration section.
2020.12.01 20.3
  • Changed table title from Virtual JTAG Settings Description to Parameter Settings for Virtual JTAG and updated the content.
  • Updated parameters in the Description of Simulation Parameters table.
  • Updated the description in the Compiling the Design section.
  • Updated the following diagrams:
    • Compilation Report
    • IDs of Virtual JTAG Instances
    • Logic Resources Utilization
  • Renamed IP from Virtual JTAG (altera_virtual_jtag) IP core to Virtual JTAG Intel® FPGA IP core.
2018.07.19 16.1
  • Updated the following terms:
    • Changed Quartus II to Intel Quartus Prime.
    • Changed SignalTap II to Signal Tap.
    • Changed megafunction to Intel FPGA IP core.
    • Changed USB Blaster to Intel FPGA Download Cable.
    • Changed ByteBlaster II to Intel FPGA Parallel Port Cable.
    • Changed ModelSim-Altera to ModelSim - Intel FPGA Edition.
  • Rebranded as Intel.

Date

Version

Changes

October 2016 2016.10.31 Removed Upgrading IP Cores section.
November 2015 2015.11.20 Corrected the flow for EXIT2_DR to SHIFT_DR in the JTAG TAP Controller State Machine figure.
July 2014 2014.07.08
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.

March 2014

2014.03.19

Updated the description of the SLD_IR_WIDTH parameter in the "Parameters for the Virtual JTAG Megafunction" table.

February 2014

2014.02.25

  • Added Document Revision History table.
  • Updated "Hub IP Configuration Register" figure.
Level Two Title