Virtual JTAG Intel® FPGA IP Core User Guide

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ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

Transaction Model of the SLD Infrastructure

In the presence of an application that requires the JTAG resource, the Intel® Quartus® Prime software automatically implements the SLD infrastructure to handle the arbitration of the JTAG resource. The communication interface between JTAG and any IP cores is transparent to the designer. All components of the SLD infrastructure, except for the JTAG TAP controller, are built using programmable logic resources.

The SLD infrastructure mimics the IR/DR paradigm defined by the JTAG protocol. Each application implements an Instruction Register, and a set of Data Registers that operate similarly to the Instruction Register and Data Registers in the JTAG standard. Note that the Instruction Register and the Data Register banks implemented by each application are a subset of the USER1 and USER0 Data Register chains. The SLD infrastructure consists of three subsystems: the JTAG TAP controller, the SLD hub, and the SLD nodes.

The SLD hub acts as the arbiter that routes the TDI pin connection between each SLD node, and is a state machine that mirrors the JTAG TAP controller state machine.

The SLD nodes represent the communication channels for the end applications. Each instance of IP requiring a JTAG communication resource, such as the Signal Tap logic analyzer, would have its own communication channel in the form of a SLD node interface to the SLD hub. Each SLD node instance has its own Instruction Register and bank of DR chains. Up to 255 SLD nodes can be instantiated, depending on resources available in your device.

Together, the sld_hub and the SLD nodes form a virtual JTAG scan chain within the JTAG protocol. It is virtual in the sense that both the Instruction Register and DR transactions for each SLD node instance are encapsulated within a standard DR scan shift of the JTAG protocol.

The Instruction Register and Data Registers for the SLD nodes are a subset of the USER1 and USER0 Data Registers. Because the SLD Node IR/DR register set is not directly part of the IR/DR register set of the JTAG protocol, the SLD node Instruction Register and Data Register chains are known as Virtual IR (VIR) and Virtual DR (VDR) chains. The figure below shows the transaction model of the SLD infrastructure.

Figure 6. Extension of the JTAG Protocol for PLD Applications
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