Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

18.6.5. EMAC Initialization and Configuration

The following EMAC configuration operations can be performed after DMA initialization. If the EMAC initialization and configuration is done before the DMA is set up, then enable the MAC receiver (last step below) only after the DMA is active. Otherwise, the received frame could fill the RX FIFO buffer and overflow.

  1. Program the GMII Address Register (offset 0x10) for controlling the management cycles for the external PHY. Bits[15:11] of the GMII Address Register are written with the Physical Layer Address of the PHY before reading or writing. Bit 0 indicates if the PHY is busy and is set before reading or writing to the PHY management interface. †
  2. Read the 16‑bit data of the GMII Data Register from the PHY for link up, speed of operation, and mode of operation, by specifying the appropriate address value in bits[15:11] of the GMII Address Register. †
  3. Provide the MAC address registers (MAC Address0 High Register through MAC Address15 High Register and MAC Address0 Low Register through MAC Address15 Low Register).
  4. Program the Hash Table Registers 0 through 7 (offset 0x500 to 0x51C).
  5. Program the following fields to set the appropriate filters for the incoming frames in the MAC Frame Filter Register: †
    • Receive All †
    • Promiscuous mode †
    • Hash or Perfect Filter †
    • Unicast, multicast, broadcast, and control frames filter settings †
  6. Program the following fields for proper flow control in the Flow Control Register: †
    • Pause time and other pause frame control bits †
    • Receive and Transmit Flow control bits †
    • Flow Control Busy/Backpressure Activate †
  7. Program the Interrupt Mask Register bits, as required and if applicable for your configuration. †
  8. Program the appropriate fields in MAC Configuration Register to configure receive and transmit operation modes. After basic configuration is written, set bit 3 (TE) and bit 2 (RE) in this register to enable the receive and transmit state machines. †
    Note: Do not change the configuration (such as duplex mode, speed, port, or loopback) when the EMAC DMA is actively transmitting or receiving. Software should change these parameters only when the EMAC DMA transmitter and receiver are not active.