Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

12.4.2.1. RAM and ECC Memory Organization Example

The on-chip RAM and DMA have a memory organization that is byte-writeable, where every byte of data requires 5 bits of ECC.

The tables below shows the memory organization of the byte-writable memory with a 64-bit data size and 5 bits of ECC data.

Table 113.  Organization of Byte-Writeable Memory with 64-bit Data Size
Address RAM Bits
[63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0]
0x0 data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0]
0x8 data[15] data[14] data[13] data[12] data[11] data[10] data[9] data[8]
Table 114.  Memory Organization of 5-Bit ECC Data
Address ECC Memory Bits
[31:29] [28:24] [23:21] [20:16] [15:13] [12:8] [7:5] [4:0]
0x0 0x0 ecc_data[3] 0x0 ecc_data[2] 0x0 ecc_data[1] 0x0 ecc_data[0]
0x4 0x0 ecc_data[7] 0x0 ecc_data[6] 0x0 ecc_data[5] 0x0 ecc_data[4]
0x8 0x0 ecc_data[11] 0x0 ecc_data[10] 0x0 ecc_data[9] 0x0 ecc_data[8]
0xC 0x0 ecc_data[15] 0x0 ecc_data[14] 0x0 ecc_data[13] 0x0 ecc_data[12]