Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

10.3.3. Cortex*-A9 Processor

Each Cortex*-A9 processor includes the following hardware blocks:

  • Arm* NEON* single instruction, multiple data (SIMD) coprocessor with vector floating‑point (VFP) v3 double‑precision floating point unit for media and signal processing acceleration
    • Single‑ and double‑precision IEEE‑754 floating point math support
    • Integer and polynomial math support
  • Level 1 (L1) cache with parity checking
    • 32 KB four‑way set‑associative instruction cache
    • 32 KB four‑way set‑associative data cache
  • CoreSight* Program Trace Macrocell (PTM) supporting instruction trace

Each Cortex*-A9 processor supports the following features:

  • Dual‑issue superscalar pipeline with advanced branch prediction
  • Out‑of‑order (OoO) dispatch and speculative instruction execution
  • 2.5 million instructions per second (MIPS) per MHz, based on the Dhrystone 2.1 benchmark
  • 2048-entry Branch Target Address Cache (BTAC)
  • 512‑entry translation lookaside buffer (TLB)
  • 64-entry instruction micro-TLB
  • TrustZone security extensions
  • Configurable data endianness
  • Jazelle* DBX Extensions for byte‑code dynamic compiler support
  • The Cortex*-A9 processor architecture supports the following instruction sets:
    • The Arm* v7‑A performance‑optimized instruction set
    • The memory‑optimized Thumb*‑2 mixed instruction set
      • Improves energy efficiency
      • 31% smaller memory footprint
      • 38% faster than the original Thumb instruction set
    • The Thumb instruction set—supported for legacy applications
  • Each processor core in the Intel® HPS includes an MMU to support the memory management requirements of common modern operating systems.

The Cortex*-A9 processors are designated CPU0 and CPU1.