Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

10.3.12.2.1. GIC Interrupt Map for the Arria 10 SoC HPS

Note: To ensure that you are using the correct GIC interrupt number, your code should refer to the symbolic interrupt name, as shown in the Interrupt Name column. Symbolic interrupt names are defined in a header file distributed with the source installation for your operating system.
Note: cpu<0..1>_deflags<0..6> are the Cortex* -A9 processor's data engine output flags.
Table 88.  GIC Interrupt Map

GIC Interrupt Number

Source Block

Interrupt Name

Combined Interrupts

Triggering

32

System Manager

DERR_Global

This interrupt combines: ddr_derr,

dma_derr,

emac0_tx_derr,

emac0_rx_derr,

emac1_tx_derr,

emac1_rx_derr,

emac2_tx_derr,

emac2_rx_derr,

usb0_derr,

usb1_derr,

sdmmc_porta_derr,

sdmmc_portb_derr,

nandr_derr,

nandw_derr,

nande_derr,

qspi_derr,

ram_derr,

and l2_derr.

Level

33

System Manager

cpux_parityfail

This interrupt combines: cpu0_parityfail_BTAC,

cpu0_parityfail_GHB,

cpu0_parityfail_I_Tag,

cpu0_parityfail_I_Data,

cpu0_parityfail_TLB,

cpu0_parityfail_D_Outer,

cpu0_parityfail_D_Tag,

cpu0_parityfail_D_Data,

cpu1_parityfail_BTAC,

cpu1_parityfail_GHB,

cpu1_parityfail_I_Tag,

cpu1_parityfail_I_Data,

cpu1_parityfail_TLB,

cpu1_parityfail_D_Outer,

cpu1_parityfail_D_Tag,

cpu1_parityfail_D_Data,

scu_parityfail0,

and scu_parityfail1.

Level

34

System Manager

SERR_Global

This interrupt combines: ddr_serr,

dma_serr,

emac0_tx_serr,

emac0_rx_serr,

emac1_tx_serr,

emac1_rx_serr,

emac2_tx_serr,

emac2_rx_serr,

usb0_serr,

usb1_serr,

sdmmc_porta_serr,

sdmmc_portb_serr,

nandr_serr,

nandw_serr,

nande_serr,

qspi_serr,

ram_serr,

and l2_serr.

Level

35

CortexA9_0

cpu0_deflags0

 -

Level

36

CortexA9_0

cpu0_deflags1

 -

Level

37

CortexA9_0

cpu0_deflags2

 -

Level

38

CortexA9_0

cpu0_deflags3

 -

Level

39

CortexA9_0

cpu0_deflags4

 -

Level

40

CortexA9_0

cpu0_deflags5

 -

Level

41

CortexA9_0

cpu0_deflags6

 -

Level

42

CortexA9_1

cpu1_deflags0

 -

Level

43

CortexA9_1

cpu1_deflags1

 -

Level

44

CortexA9_1

cpu1_deflags2

 -

Level

45

CortexA9_1

cpu1_deflags3

 -

Level

46

CortexA9_1

cpu1_deflags4

 -

Level

47

CortexA9_1

cpu1_deflags5

 -

Level

48

CortexA9_1

cpu1_deflags6

 -

Level

49

SCU

scu_ev_abort

 -

Edge-triggered

50

L2-Cache

l2_combined_IRQ

This interrupt combines: DECERRINTR,

ECNTRINTR,

ERRRDINTR,

ERRRTINTR,

ERRWDINTR,

ERRWTINTR,

PARRDINTR,

PARRTINTR,

and SLVERRINTR

Level

51

FPGA

F2S_FPGA_IRQ0

 -

Level or Edge

52

FPGA

F2S_FPGA_IRQ1

 -

Level or Edge

53

FPGA

F2S_FPGA_IRQ2

 -

Level or Edge

54

FPGA

F2S_FPGA_IRQ3

 -

Level or Edge

55

FPGA

F2S_FPGA_IRQ4

 -

Level or Edge

56

FPGA

F2S_FPGA_IRQ5

 -

Level or Edge

57

FPGA

F2S_FPGA_IRQ6

 -

Level or Edge

58

FPGA

F2S_FPGA_IRQ7

 -

Level or Edge

59

FPGA

F2S_FPGA_IRQ8

 -

Level or Edge

60

FPGA

F2S_FPGA_IRQ9

 -

Level or Edge

61

FPGA

F2S_FPGA_IRQ10

 -

Level or Edge

62

FPGA

F2S_FPGA_IRQ11

 -

Level or Edge

63

FPGA

F2S_FPGA_IRQ12

 -

Level or Edge

64

FPGA

F2S_FPGA_IRQ13

 -

Level or Edge

65

FPGA

F2S_FPGA_IRQ14

 -

Level or Edge

66

FPGA

F2S_FPGA_IRQ15

 -

Level or Edge

67

FPGA

F2S_FPGA_IRQ16

 -

Level or Edge

68

FPGA

F2S_FPGA_IRQ17

 -

Level or Edge

69

FPGA

F2S_FPGA_IRQ18

 -

Level or Edge

70

FPGA

F2S_FPGA_IRQ19

 -

Level or Edge

71

FPGA

F2S_FPGA_IRQ20

 -

Level or Edge

72

FPGA

F2S_FPGA_IRQ21

 -

Level or Edge

73

FPGA

F2S_FPGA_IRQ22

 -

Level or Edge

74

FPGA

F2S_FPGA_IRQ23

 -

Level or Edge

75

FPGA

F2S_FPGA_IRQ24

 -

Level or Edge

76

FPGA

F2S_FPGA_IRQ25

 -

Level or Edge

77

FPGA

F2S_FPGA_IRQ26

 -

Level or Edge

78

FPGA

F2S_FPGA_IRQ27

 -

Level or Edge

79

FPGA

F2S_FPGA_IRQ28

 -

Level or Edge

80

FPGA

F2S_FPGA_IRQ29

 -

Level or Edge

81

FPGA

F2S_FPGA_IRQ30

 -

Level or Edge

82

FPGA

F2S_FPGA_IRQ31

 -

Level or Edge

83

FPGA

F2S_FPGA_IRQ32

 -

Level or Edge

84

FPGA

F2S_FPGA_IRQ33

 -

Level or Edge

85

FPGA

F2S_FPGA_IRQ34

 -

Level or Edge

86

FPGA

F2S_FPGA_IRQ35

 -

Level or Edge

87

FPGA

F2S_FPGA_IRQ36

 -

Level or Edge

88

FPGA

F2S_FPGA_IRQ37

 -

Level or Edge

89

FPGA

F2S_FPGA_IRQ38

 -

Level or Edge

90

FPGA

F2S_FPGA_IRQ39

 -

Level or Edge

91

FPGA

F2S_FPGA_IRQ40

 -

Level or Edge

92

FPGA

F2S_FPGA_IRQ41

 -

Level or Edge

93

FPGA

F2S_FPGA_IRQ42

 -

Level or Edge

94

FPGA

F2S_FPGA_IRQ43

 -

Level or Edge

95

FPGA

F2S_FPGA_IRQ44

 -

Level or Edge

96

FPGA

F2S_FPGA_IRQ45

 -

Level or Edge

97

FPGA

F2S_FPGA_IRQ46

 -

Level or Edge

98

FPGA

F2S_FPGA_IRQ47

 -

Level or Edge

99

FPGA

F2S_FPGA_IRQ48

 -

Level or Edge

100

FPGA

F2S_FPGA_IRQ49

 -

Level or Edge

101

FPGA

F2S_FPGA_IRQ50

 -

Level or Edge

102

FPGA

F2S_FPGA_IRQ51

 -

Level or Edge

103

FPGA

F2S_FPGA_IRQ52

 -

Level or Edge

104

FPGA

F2S_FPGA_IRQ53

 -

Level or Edge

105

FPGA

F2S_FPGA_IRQ54

 -

Level or Edge

106

FPGA

F2S_FPGA_IRQ55

 -

Level or Edge

107

FPGA

F2S_FPGA_IRQ56

 -

Level or Edge

108

FPGA

F2S_FPGA_IRQ57

 -

Level or Edge

109

FPGA

F2S_FPGA_IRQ58

 -

Level or Edge

110

FPGA

F2S_FPGA_IRQ59

 -

Level or Edge

111

FPGA

F2S_FPGA_IRQ60

 -

Level or Edge

112

FPGA

F2S_FPGA_IRQ61

 -

Level or Edge

113

FPGA

F2S_FPGA_IRQ62

 -

Level or Edge

114

FPGA

F2S_FPGA_IRQ63

 -

Level or Edge

115

DMA

dma_IRQ0

 -

Level

116

DMA

dma_IRQ1

 -

Level

117

DMA

dma_IRQ2

 -

Level

118

DMA

dma_IRQ3

 -

Level

119

DMA

dma_IRQ4

 -

Level

120

DMA

dma_IRQ5

 -

Level

121

DMA

dma_IRQ6

 -

Level

122

DMA

dma_IRQ7

 -

Level

123

DMA

dma_irq_abort

 -

Level

124

EMAC0

emac0_IRQ

This interrupt combines: sbd_intr_o

and lpi_intr_o.

 Level

125

EMAC1

emac1_IRQ

This interrupt combines: sbd_intr_o

and lpi_intr_o.

 Level

126

EMAC2

emac2_IRQ

This interrupt combines: sbd_intr_o

and lpi_intr_o.

 Level

127

USB0

usb0_IRQ

 -

Level

128

USB1

usb1_IRQ

 -

Level

129

SDRAM scheduler

HMC_error

 -

Level

130

SDMMC

sdmmc_IRQ

 -

Level

131

NAND

nand_IRQ

 -

Level

132

QSPI

qspi_IRQ

 -

Level

133

SPI0 master

spim0_IRQ

This interrupt combines: ssi_txe_intr,

ssi_txo_intr,

ssi_rxf_intr,

ssi_rxo_intr,

ssi_rxu_intr,

and ssi_mst_intr.

Level

134

SPI1 master

spim1_IRQ

This interrupt combines: ssi_txe_intr,

ssi_txo_intr,

ssi_rxf_intr,

ssi_rxo_intr,

ssi_rxu_intr,

and ssi_mst_intr.

Level

135

SPI0 slave

spis0_IRQ

This interrupt combines: ssi_txe_intr,

ssi_txo_intr,

ssi_rxf_intr,

ssi_rxo_intr,

ssi_rxu_intr,

and ssi_mst_intr.

Level

136

SPI1 slave

spis1_IRQ

This interrupt combines: ssi_txe_intr,

ssi_txo_intr,

ssi_rxf_intr,

ssi_rxo_intr,

ssi_rxu_intr,

and ssi_mst_intr.

Level

137

I2C0

i2c0_IRQ

This interrupt combines: ic_rx_under_intr,

ic_rx_full_intr,

ic_tx_over_intr,

ic_tx_empty_intr,

ic_rd_req_intr,

ic_tx_abrt_intr,

ic_rx_done_intr,

ic_activity_intr,

ic_stop_det_intr,

ic_start_det_intr,

and ic_gen_call_intr.

Level

138

I2C1

i2c1_IRQ

This interrupt combines: ic_rx_under_intr,

ic_rx_full_intr,

ic_tx_over_intr,

ic_tx_empty_intr,

ic_rd_req_intr,

ic_tx_abrt_intr,

ic_rx_done_intr,

ic_activity_intr,

ic_stop_det_intr,

ic_start_det_intr,

and ic_gen_call_intr.

Level

139

I2C2 (can be used with EMAC0)

i2c2_IRQ

This interrupt combines: ic_rx_under_intr,

ic_rx_full_intr,

ic_tx_over_intr,

ic_tx_empty_intr,

ic_rd_req_intr,

ic_tx_abrt_intr,

ic_rx_done_intr,

ic_activity_intr,

ic_stop_det_intr,

ic_start_det_intr,

and ic_gen_call_intr.

Level

140

I2C3 can be used with EMAC1)

i2c3_IRQ

This interrupt combines: ic_rx_under_intr,

ic_rx_full_intr,

ic_tx_over_intr,

ic_tx_empty_intr,

ic_rd_req_intr,

ic_tx_abrt_intr,

ic_rx_done_intr,

ic_activity_intr,

ic_stop_det_intr,

ic_start_det_intr,

and ic_gen_call_intr.

Level

141

I2C4 (can be used with EMAC2)

i2c4_IRQ

This interrupt combines: ic_rx_under_intr,

ic_rx_full_intr,

ic_tx_over_intr,

ic_tx_empty_intr,

ic_rd_req_intr,

ic_tx_abrt_intr,

ic_rx_done_intr,

ic_activity_intr,

ic_stop_det_intr,

ic_start_det_intr,

and ic_gen_call_intr.

Level

142

UART0

uart0_IRQ

 -

Level

143

UART1

uart1_IRQ

 -

Level

144

GPIO0

gpio0_IRQ

 -

Level

145

GPIO1

gpio1_IRQ

 -

Level

146

GPIO2

gpio2_IRQ

 -

Level

147

Timer0

timer_l4sp_0_IRQ

This interrupt combines: TIMINT1 and TIMINT2

Level

148

Timer1

timer_l4sp_1_IRQ

This interrupt combines: TIMINT1 and TIMINT2.

Level

149

Timer2

timer_osc1_0_IRQ

This interrupt combines: TIMINT1 and TIMINT2.

Level

150

Timer3

timer_osc1_1_IRQ

This interrupt combines: TIMINT1 and TIMINT2.

Level

151

Watchdog0

wdog0_IRQ

 -

Level

152

Watchdog1

wdog1_IRQ

 -

Level

153

Clock Manager

clkmgr_IRQ

 -

Level

154

Reset Manager

restmgr_IRQ

 -

Level

155

FPGA Manager

fpga_man_IRQ

 -

Level

156

CoreSight

nCTIIRQ[0]

 -

Level

157

CoreSight

nCTIIRQ[1]

 -

Level

158

Security Manager

SEC_MGR_INTR

 -

Level

159

L2-Cache

DATABWERR

 -

Edge-triggered