External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

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Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction 3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture 4. Intel Agilex® 7 M-Series FPGA EMIF IP – End-User Signals 5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support 7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support 8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure 10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization 11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging 12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
1.1. Release Information
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction x
2.1. Intel Agilex® 7 M-Series EMIF IP Protocol and Feature Support 2.2. Intel Agilex® 7 M-Series EMIF IP Design Flow 2.3. Intel Agilex® 7 M-Series EMIF IP Design Checklist
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Intel Agilex® 7 M-Series EMIF Architecture: Introduction 3.2. Intel Agilex® 7 M-Series EMIF Sequencer 3.3. Intel Agilex® 7 M-Series EMIF Controller
3.1. Intel Agilex® 7 M-Series EMIF Architecture: Introduction x
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. DDR4 Pin Placement 3.1.3.2. DDR5 Pin Placement 3.1.3.3. LPDDR5 Pin Placement 3.1.3.4. I/O Sub-Bank Usage
3.2. Intel Agilex® 7 M-Series EMIF Sequencer x
3.2.1. Intel Agilex® 7 M-Series Mailbox Structure and Register Definitions
3.3. Intel Agilex® 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
4. Intel Agilex® 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. Intel Agilex® 7 M-Series EMIF IP for DDR4 Interfaces 4.2. Intel Agilex® 7 M-Series EMIF IP for DDR5 Interfaces 4.3. Intel Agilex® 7 M-Series EMIF IP for LPDDR5 Interfaces
4.1. Intel Agilex® 7 M-Series EMIF IP for DDR4 Interfaces x
4.1.1. ref_clk for EMIF 4.1.2. core_init_n for EMIF 4.1.3. usr_async_clk for EMIF 4.1.4. usr_clk for EMIF 4.1.5. usr_rst_n for EMIF 4.1.6. s0_axi4 for EMIF 4.1.7. mem for EMIF 4.1.8. oct for EMIF 4.1.9. s0_axil_clk for EMIF 4.1.10. s0_axil_rst_n for EMIF 4.1.11. s0_axil for EMIF
4.2. Intel Agilex® 7 M-Series EMIF IP for DDR5 Interfaces x
4.2.1. ref_clk for EMIF 4.2.2. core_init_n for EMIF 4.2.3. usr_async_clk for EMIF 4.2.4. usr_clk for EMIF 4.2.5. usr_rst_n for EMIF 4.2.6. s0_axi4 for EMIF 4.2.7. mem for EMIF 4.2.8. oct for EMIF 4.2.9. s0_axil_clk for EMIF 4.2.10. s0_axil_rst_n for EMIF 4.2.11. s0_axil for EMIF
4.3. Intel Agilex® 7 M-Series EMIF IP for LPDDR5 Interfaces x
4.3.1. ref_clk for EMIF 4.3.2. core_init_n for EMIF 4.3.3. usr_async_clk for EMIF 4.3.4. usr_clk for EMIF 4.3.5. usr_rst_n for EMIF 4.3.6. s0_axi4 for EMIF 4.3.7. mem for EMIF 4.3.8. oct for EMIF 4.3.9. s0_axil_clk for EMIF 4.3.10. s0_axil_rst_n for EMIF 4.3.11. s0_axil for EMIF
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR4 6.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.3. DDR4 Board Design Guidelines
6.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR4 x
6.1.1. Intel Agilex 7 M-Series FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions 6.1.2. Intel Agilex 7 M-Series FPGA EMIF IP Parameter Descriptions (DDR4)
6.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 6.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 6.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP 6.2.4. Pin Placements for Intel Agilex® 7 M-Series FPGA DDR4 EMIF IP
6.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
6.2.1.1. Estimating Pin Requirements 6.2.1.2. DIMM Options 6.2.1.3. Maximum Number of Interfaces
6.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
6.2.2.1. OCT 6.2.2.2. PLL
6.2.4. Pin Placements for Intel Agilex® 7 M-Series FPGA DDR4 EMIF IP x
6.2.4.1. Address and Command Pin Placement for DDR4 6.2.4.2. DDR4 Data Width Mapping 6.2.4.3. General Guidelines 6.2.4.4. x4 DIMM Implementation 6.2.4.5. Specific Pin Connection Requirements 6.2.4.6. Command and Address Signals 6.2.4.7. Clock Signals 6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. DDR4 Board Design Guidelines x
6.3.1. Terminations for DDR4 with Intel Agilex® 7 M-Series Devices 6.3.2. General Layout Routing Guidelines 6.3.3. Reference Stackup 6.3.4. Intel Agilex® 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.3.1. Terminations for DDR4 with Intel Agilex® 7 M-Series Devices x
6.3.1.1. Dynamic On-Chip Termination (OCT) 6.3.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.3.1.3. Choosing Terminations on Intel Agilex® 7 M-Series FPGA Devices 6.3.1.4. On-Chip Termination Recommendations for Intel Agilex® 7 M-Series FPGA Devices
6.3.4. Intel Agilex® 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.3.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.3.4.2. Skew Matching Guidelines for DIMM Configurations 6.3.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.3.5.1. Single Rank x 8 Discrete (Component) Topology 6.3.5.2. Single Rank x 16 Discrete (Component) Topology 6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines x
6.3.5.6.1. DDR4 Byte Lane Swapping 6.3.5.6.2. DDR4 Address and Command and CLK Lane 6.3.5.6.3. DDR4 Interface x8 Data Lane 6.3.5.6.4. DDR4 Interface x4 Data Lane
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR5 7.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning
7.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR5 x
7.1.1. Intel Agilex 7 M-Series FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions 7.1.2. Intel Agilex 7 M-Series FPGA EMIF IP Parameter Descriptions (DDR5)
7.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP x
7.2.3.1. General Guidelines 7.2.3.2. x4 DIMM Implementation Data Bus Connection Mapping Flow 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM/DBI, and Optional ECC Signals
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for LPDDR5 8.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning
8.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for LPDDR5 x
8.1.1. Intel Agilex 7 M-Series FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions 8.1.2. Intel Agilex 7 M-Series FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR5
8.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 8.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP
8.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. DIMM Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Generating Traffic with the Test Engine IP
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex® 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

7.2.3.2. x4 DIMM Implementation

DIMMS using a x4 DQS configuration require remapping of the DQS signals to achieve compatibility between the EMIF IP and the JEDEC standard DIMM socket connections.

The necessary remapping is shown in the table below. You can implement this DQS remapping in either RTL logic or in your schematic wiring connections.

Table 89.  Mapping of DQS Signals Between DIMM and the EMIF IP
DIMM   Intel® Quartus® Prime EMIF IP
DQS0_A DQ[3:0]_A   DQS0 DQ[3:0]_A
DQS5_A DQ[7:4]_A   DQS1 DQ[7:4]_A
DQS1_A DQ[11:8]_A   DQS2 DQ[11:8]_A
DQS6_A DQ[15:12]_A   DQS3 DQ[15:12]_A
DQS2_A DQ[19:16]_A   DQS4 DQ[19:16]_A
DQS7_A DQ[23:20]_A   DQS5 DQ[23:20]_A
DQS3_A DQ[27:24]_A   DQS6 DQ[27:24]_A
DQS8_A DQ[31:28]_A   DQS7 DQ[31:28]_A
DQS4_A CB[3:0]_A   DQS8 CB[3:0]_A
DQS9_A CB[7:4]_A   DQS9 CB[7:4]_A
DQS0_B DQ[3:0]_B   DQS10 DQ[3:0]_B
DQS5_B DQ[7:4]_B   DQS11 DQ[7:4]_B
DQS1_B DQ[11:8]_B   DQS12 DQ[11:8]_B
DQS6_B DQ[15:12]_B   DQS13 DQ[15:12]_B
DQS2_B DQ[19:16]_B   DQS14 DQ[19:16]_B
DQS7_B DQ[23:20]_B   DQS15 DQ[23:20]_B
DQS3_B DQ[27:24]_B   DQS16 DQ[27:24]_B
DQS8_B DQ[31:28]_B   DQS17 DQ[31:28]_B
DQS4_B CB[3:0]_B   DQS18 CB[3:0]_B
DQS9_B CB[7:4]_B   DQS19 CB[7:4]_B

Data Bus Connection Mapping Flow

  1. Connect all FPGA DQ pins accordingly to DIMM DQ pins. No remapping is required.
  2. DQS/DQSn remapping is required either on the board schematics or in the RTL code.

When designing a board to support x4 DQS groups, Intel® recommends that you make it compatible for x8 mode, for the following reasons:

  • Provides the flexibility of x4 and x8 DIMM support.
  • Allows use of x8 DQS group connectivity rules.
  • Allows use of x8 timing rules for matching. Adhere to x4/x8 interoperability rules when designing a DIMM interface, even if the primary use case is to support x4 DIMMs only, because doing so facilitates debug and future migration capabilities. Regardless, the rules for length matching for two nibbles in a x4 interface must match those of the signals for a corresponding x8 interface, as the data terminations are turned on and off at the same time for both x4 DQS groups in an I/O lane. If the two x4 DQS groups were to have significantly different trace delays, it could adversely affect signal integrity. Trace delays for two nibbles packed within the IO12 lanes are matched using the same guidelines as a single x8 byte lane.
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