F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 12/17/2021
Public

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3.4. Compiling the Design Example

  1. Navigate to <project_dir>/pcie_avst_f_0_example_design/ and open pcie_ed.qpf.
  2. On the Processing menu, select Start Compilation.
  3. Open the example design project.
  4. Compile the example design project examine the design compilation result like resource utilization and timing result.
  5. Close your example design project.
    Note: You cannot change the PCIe pin allocations in the Intel® Quartus® Prime project. However, to ease PCB routing, you can take advantage of the lane reversal and polarity inversion features supported by this IP.