F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 12/17/2021
Public

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2.5.2.3. Completion

The Completion submodule stores the necessary header information from the incoming MRd instruction and repackages the acquired information into a CplD header. The CplD header is released together with the fetched data from targeted Segram.