F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 12/17/2021
Public

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2.2.2.2. Read Write Module

Prepare the Avalon-MM write or read sequence for the Avalon-MM Interface.
  • Write sequence: Data is aligned by the Barrel Shifter and passed to aligned data FIFO. The write state machine extracts the address, burst count, FBE/LBE and generate Avalon-MM write command. The command is then stored to the Avalon-MM command FIFO and eventually passed to the Avalon-MM Interface. Maximum write burst count allowed is 8 as decided from the aligned data FIFO depth.
  • Read sequence: The read state machine decodes the combination of Type1 read and Type2 read based on the PREPROC CMD. Next it generates the Avalon-MM command accordingly for each Type1 or Type2 read. Concurrently, the CPL command is generated for each AVMM read command and stored to the CPL CMD FIFO. In the event of waitrequest by the MEM device, Avalon-MM command FIFO can hold up to 16 data cycles.