F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 12/17/2021
Public

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Document Table of Contents

2.1. Programmed Input/Output Design Example

Figure 1. PCIe Gen3/Gen4 x16 Design Example Variant Block Diagram

Figure 2. PCIe Gen3/Gen4 x8x8 Design Example Variant

Figure 3. PCIe Gen3/Gen4 x8 Design Example Variant

The PCIe F-Tile Design Example is designed to highlight the application of PCIe Gen4 in F-Tile. The PCIe IP run up to 500MHz at user interface with the maximum data width of 512 bits for Gen4 x16 and 256 bits for each of the two Gen4 x8 ports.

The clock frequency supplied from the coreclkout_hip is limited to 500 MHz.

The Design Example consists of 3 main components to display the intended design
  • F-Tile Avalon-ST IP for PCI Express Hard IP (DUT)
  • Programmable I/O Application (PIO)
  • On-Chip Memory (MEM)

The PIO design example performs memory transfers from a host processor to a target device. In this example, the host processor requests single-dword MemRd and MemWr TLPs.

The PIO design example automatically creates the required files to simulate and compile in the Intel® Quartus® Prime software. The design example covers a wide range of parameters. However, it does not cover all possible parameterizations of the F-Tile Hard IP for PCIe.